Intel 8XC196K Series User Manual page 246

EPA_MASK
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with
the multiplexed EPA x interrupt.
15
CA, Jx —
7
0VR2
15
K x EPA4
7
OVR2
Bit
Number
†
15:0 Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the interrupt
mask register (INT_MASK.0 = 1).
†
Bits 2–5 and 12–15 are reserved on the 8XC196CA, J x devices. For compatibility with future
devices, write zeros to these bits.
Figure 10-12. EPA Interrupt Mask (EPA_MASK) Register
EPA_MASK1
The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated
with the EPA x interrupt.
7
— —
Bit
Number
7:4 Reserved; for compatibility with future devices, write zeros to these bits.
3:0 Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the
interrupt mask register (INT_MASK.0 = 1).
Figure 10-13. EPA Interrupt Mask 1 (EPA_MASK1) Register
— — —
OVR3 — —
EPA5 EPA6 EPA7
OVR3 OVR4 OVR5
Function
— —
Function
EVENT PROCESSOR ARRAY (EPA)
Address:
Reset State:
EPA8 EPA9
— —
EPA8 EPA9
OVR6 OVR7
Reset State:
COMP0 COMP1 OVRTM1
1FA0H
0000H
8
OVR0 OVR1
0
OVR8 OVR9
8
OVR0 OVR1
0
OVR8 OVR9
Address: 1FA4H
00H
0
OVRTM2
10-27