Intel 8XC196K Series User Manual page 605

8XC196K x, J x , CA USER'S MANUAL
USFR
USFR
The unerasable PROM (USFR) register contains two bits that disable external fetches of data and
instructions and another that detects a failed oscillator. These bits can be programmed, but cannot be
erased.
WARNING: These bits can be programmed, but can never be erased. Programming these bits makes
dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot
be returned to Intel for failure analysis.
7
— —
Bit Bit
Number Mnemonic
7:4 —
3 DEI
2 DED
1 —
0 OFD
C-78
— —
Reserved; always write as zeros.
Disable External Instruction Fetch
Setting this bit prevents the bus controller from executing external
instruction fetches. Any attempt to load an external address initiates a
reset.
Disable External Data Fetch
Setting this bit prevents the bus controller from executing external data
reads and writes. Any attempt to access data through the bus controller
initiates a reset.
Reserved; always write as zero.
Oscillator Fail Detect
Setting this bit enables the device to detect a failed oscillator and reset
itself. (In EPROM packages, this bit can be erased.)
Address:
Reset State:
DEI DED
Function
1FF6H
XXH
0
— OFD