Regaining Bus Control (8Xc196K X Only); Bus-Control Modes; Standard Bus-Control Mode - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL

15.5.4 Regaining Bus Control (8XC196K x Only)

While HOLD# is asserted, the device continues executing code until it needs to access the exter-
nal bus. If executing from internal memory, it continues until it needs to perform an external
memory cycle. If executing from external memory, it continues executing until the queue is emp-
ty or until it needs to perform an external data cycle. As soon as it needs to access the external
bus, the device asserts BREQ# and waits for the external device to deassert HOLD#. After assert-
ing BREQ#, the device cannot respond to any interrupt requests, including NMI, until the exter-
nal device deasserts HOLD#. One state time after HOLD# goes high, the device deasserts
HLDA# and, with no delay, resumes control of the bus.
If the device is reset while in hold, bus contention can occur. For example, a CPU-only device
would try to fetch the chip configuration byte from external memory after RESET# was brought
high. Bus contention would occur because both the external device and the device would attempt
to access memory. One solution is to use the RESET# signal as the system reset; then all bus mas-
ters (including the device) are reset at once. Chapter 13, "Minimum Hardware Considerations,"
shows system reset circuit examples.

15.6 BUS-CONTROL MODES

The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated
during external read and write cycles. Table 15-5 lists the four bus-control modes and shows the
CCR0.3 and CCR0.2 settings for each.
.
Bus-control Mode

Standard Bus-control Mode

Write Strobe Mode
Address Valid Strobe Mode
Address Valid with Write Strobe Mode
†
The BHE# and WRH# pins are not implemented on the 87C196CA, 8XC196J x devices.
15.6.1 Standard Bus-control Mode
In the standard bus-control mode, the device generates the standard bus-control signals: ALE,
RD#, WR#, and BHE# (see Figure 15-9). ALE is asserted while the address is driven, and it can
be used to latch the address externally. RD# is asserted for every external memory read, and WR#
is asserted for every external memory write. When asserted, BHE# selects the bank of memory
that is addressed by the high byte of the data bus.
15-20
Table 15-5. Bus-control Mode
Bus-control Signals
ALE, RD#, WR#, BHE#
ALE, RD#, WRL#, WRH#
ADV#, RD#, WR#, BHE#
ADV#, RD#, WRL#, WRH#
CCR0.3
(ALE)
†
1
†
1
†
0
†
0
CCR0.2
(WR)
1
0
1
0