Intel 8XC196K Series User Manual page 513

8XC196K x , J x , CA USER'S MANUAL
Name Type
EXTINT I
†
HLDA# O
†
HOLD# I
†
INST O
†
INTOUT# O
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B-12
Table B-6. Signal Descriptions (Continued)
External Interrupt
In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt
pending flag. EXTINT is sampled during phase 2 (CLKOUT high). The minimum
high time is one state time.
If the chip is in idle mode and if EXTINT is enabled, a rising edge on EXTINT
brings the chip back to normal operation, where the first action is to execute the
EXTINT service routine. After completion of the service routine, execution
resumes at the the IDLPD instruction following the one that put the device into
idle mode.
In powerdown mode, asserting EXTINT causes the chip to return to normal
operating mode. If EXTINT is enabled, the EXTINT service routine is executed.
Otherwise, execution continues at the instruction following the IDLPD
instruction that put the device into powerdown mode.
EXTINT is multiplexed with P2.2 and PROG#.
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result
of an external device asserting HOLD#.
HLDA# is multiplexed with P2.6 and CPVER.
Bus Hold Request
An external device uses this active-low input signal to request control of the
bus. This pin functions as HOLD# only if the pin is configured for its special
function (see "Bidirectional Port Pin Configurations" on page 6-10) and the bus-
hold protocol is enabled. Setting bit 7 of the window selection register enables
the bus-hold protocol.
HOLD# is multiplexed with P2.5.
Instruction Fetch
This active-high output signal is valid only during external memory bus cycles.
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector
fetches and chip configuration byte reads. INST is low during internal memory
fetches.
INST is multiplexed with P5.1 and SLPCS#.
Interrupt Output
This active-low output indicates that a pending interrupt requires use of the
external bus. If the 8XC196K x receives an interrupt request while it is in hold,
the 8XC196K x asserts INTOUT# only if it is executing from internal memory. If
the 8XC196K x needs to access external memory, it asserts BREQ# and waits
until the external device deasserts HOLD# to assert INTOUT#. If the
8XC196K x receives an interrupt request as it is going into hold (between the
time that an external device asserts HOLD# and the time that the 8XC196K x
responds with HLDA#), the 8XC196K x asserts INTOUT# and keeps it asserted
until the external device deasserts HOLD#.
INTOUT is multiplexed with P2.4 and AINC#.
Description