Internal Timing - Intel 8XC196K Series User Manual

2.4

INTERNAL TIMING

The clock circuitry (Figure 2-3) receives an input clock signal on XTAL1 provided by an external
crystal or oscillator and divides the frequency by two. The clock generators accept the divided
input frequency from the divide-by-two circuit and produce two nonoverlapping internal timing
signals, PH1 and PH2. These signals are active when high. The rising edges of PH1 and PH2 gen-
erate CLKOUT, the output of the internal clock generator (Figure 2-4). The clock circuitry routes
separate internal clock signals to the CPU and the peripherals to provide flexibility in power man-
agement. ("Reducing Power Consumption" on page 14-3 describes the power management
modes.) It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic
in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT
signal. This delay varies with temperature and voltage.
XTAL1
XTAL2
Disable Clock Input
(Powerdown)
F
OSC
Divide-by-two
Circuit
Clock
Generators
Disable
Oscillator
(Powerdown)
Figure 2-3. Clock Circuitry
ARCHITECTURAL OVERVIEW
Disable Clocks
(Powerdown)
Peripheral Clocks (PH1, PH2)
CLKOUT
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Powerdown)
A3064-02
2-7