Intel 8XC196NT Manuals

Manuals and User Guides for Intel 8XC196NT. We have 1 Intel 8XC196NT manual available for free PDF download: User Manual

Intel 8XC196NT User Manual (597 pages)

Brand: Intel | Category: Microcontrollers | Size: 3 MB

Table of Contents
4
Guide to this Manual
22
Manual Contents
24
Notational Conventions and Terminology
26
Related Documents
28
Electronic Support Systems
31
Faxback Service
31
Bulletin Board System (BBS)
32
How to Find Ap BUILDER Software and Hypertext Documents on the BBS
33
Compuserve Forums
33
World Wide Web
33
Technical Support
34
Product Literature
34
Training Classes
34
Architectural Overview
36
Typical Applications
38
Device Features
38
Block Diagram
38
CPU Control
40
Register File
40
Register Arithmetic-Logic Unit (RALU)
40
Code Execution
41
Instruction Format
41
Memory Controller
42
Interrupt Service
42
Internal Timing
43
Internal Peripherals
44
I/O Ports
45
Serial I/O (SIO) Port
45
Synchronous Serial I/O (SSIO) Port
45
Slave Port
46
Event Processor Array (EPA) and Timer/Counters
46
Analog-To-Digital Converter
47
Watchdog Timer
47
Special Operating Modes
47
Reducing Power Consumption
47
Testing the Printed Circuit Board
48
Programming the Nonvolatile Memory
48
Programming Considerations
50
Overview of the Instruction Set
52
BIT Operands
53
BYTE Operands
53
SHORT-INTEGER Operands
53
WORD Operands
54
INTEGER Operands
54
DOUBLE-WORD Operands
54
LONG-INTEGER Operands
55
QUAD-WORD Operands
55
Converting Operands
55
Conditional Jumps
55
Floating Point Operations
56
Extended Instructions
56
Addressing Modes
57
Direct Addressing
58
Immediate Addressing
58
Indirect Addressing
58
Extended Indirect Addressing
59
Indirect Addressing with Autoincrement
59
Extended Indirect Addressing with Autoincrement
59
Indirect Addressing with the Stack Pointer
60
Indexed Addressing
60
Short-Indexed Addressing
60
Long-Indexed Addressing
60
Extended Indexed Addressing
61
Zero-Indexed Addressing
61
Extended Zero-Indexed Addressing
61
Assembly Language Addressing Mode Selections
62
Direct Addressing
62
Indexed Addressing
62
Extended Addressing
62
Design Considerations for 1-Mbyte Devices
62
Software Standards and Conventions
62
Using Registers
63
Addressing 32-Bit Operands
63
Addressing 64-Bit Operands
63
Linking Subroutines
64
Software Protection Features and Guidelines
65
Memory Partitions
66
Memory Map Overview
68
Memory Partitions
68
External Memory
72
Program and Special-Purpose Memory
72
Program Memory in
72
Special-Purpose Memory
73
Reserved Memory Locations
74
Interrupt and PTS Vectors
74
Security Key
74
Chip Configuration Bytes
75
Special-Function Registers (Sfrs)
75
Memory-Mapped Sfrs
75
Peripheral Sfrs
76
Internal RAM (Code RAM)
78
Register File
79
General-Purpose Register RAM
79
Stack Pointer (SP)
79
CPU Special-Function Registers (Sfrs)
81
Windowing
82
Selecting a Window
83
Addressing a Location through a Window
84
32-Byte Windowing Example
86
Unsupported Locations Windowing Example
87
Using the Linker Locator to Set up a Window
87
Windowing and Addressing Modes
89
Remapping Internal Otprom (87C196Nt Only)
90
Fetching Code and Data in the 1-Mbyte and 64-Kbyte Modes
91
Fetching Instructions
91
Accessing Data
91
Using Extended Instructions
92
Code Fetches in the 1-Mbyte Mode
93
Code Fetches in the 64-Kbyte Mode
93
Data Fetches in the 1-Mbyte and 64-Kbyte Modes
94
Memory Configuration Examples
95
Example 1: a 64-Kbyte Mode 87C196NT System
95
Example 2: a 64-Kbyte 87C196NT System with Additional Data Storage
97
Example 3: a 1-Mbyte 87C196NT System with a 16-Bit Bus
99
Example 4: a 1-Mbyte 8XC196NT System with an 8-Bit Bus
101
Standard and Pts Interrupts
104
Overview of Interrupts
106
Interrupt Signals and Registers
108
Interrupt Sources and Priorities
109
Special Interrupts
111
Unimplemented Opcode
111
Software Trap
111
Nmi
111
External Interrupt Pins
111
Multiplexed Interrupt Sources
112
End-Of-PTS Interrupts
112
Interrupt Latency
112
Situations that Increase Interrupt Latency
113
Calculating Latency
113
Standard Interrupt Latency
114
PTS Interrupt Latency
114
Programming the Interrupts
115
Programming the Multiplexed Interrupts
116
Modifying Interrupt Priorities
119
Determining the Source of an Interrupt
121
Determining the Source of Multiplexed Interrupts
121
Initializing the Pts Control Blocks
123
Specifying the PTS Count
124
Selecting the PTS Mode
125
Single Transfer Mode
126
Block Transfer Mode
129
A/D Scan Mode
131
A/D Scan Mode Cycles
134
A/D Scan Mode Example 1
134
A/D Scan Mode Example 2
135
PWM Modes
136
PWM Toggle Mode Example
138
PWM Remap Mode Example
142
I/O Ports
148
I/O Ports Overview
150
Input-Only Port 0
150
Standard Input-Only Port Operation
151
Standard Input-Only Port Considerations
152
Bidirectional Ports 1, 2, 5, and 6
152
Bidirectional Port Operation
154
Bidirectional Port Pin Configurations
158
Bidirectional Port Pin Configuration Example
159
Bidirectional Port Considerations
160
Design Considerations for External Interrupt Inputs
163
Bidirectional Ports 3 and 4 (Address/Data Bus)
163
Bidirectional Ports 3 and 4 (Address/Data Bus) Operation
164
Using Ports 3 and 4 as I/O
166
Design Considerations for Ports 3 and 4
167
Eport
167
EPORT Operation
168
Reset
170
Output Enable
170
Complementary Output Mode
170
Open-Drain Output Mode
170
Input Mode
172
Configuring EPORT Pins
173
Configuring EPORT Pins for Extended-Address Functions
173
Configuring EPORT Pins for I/O
173
EPORT Considerations
174
EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
174
EP_REG Settings for Pins Configured as Extended-Address Signals
174
EPORT Status During Instruction Execution
175
Design Considerations
175
Serial I/O (Sio) Port
176
Serial I/O (Sio) Port Functional Overview
178
Serial I/O Port Signals and Registers
179
Serial Port Modes
181
Synchronous Mode (Mode 0)
181
Asynchronous Modes (Modes 1, 2, and 3)
182
Mode 1
182
Mode 2
183
Mode 3
184
Mode 2 and 3 Timings
184
Multiprocessor Communications
184
Programming the Serial Port
185
Configuring the Serial Port Pins
185
Programming the Control Register
185
Programming the Baud Rate and Clock Source
185
Enabling the Serial Port Interrupts
188
Determining Serial Port Status
189
Programming Example Using an Interrupt-Driven Routine
190
Synchronous Serial I/O (Ssio) Port
194
Synchronous Serial I/O (Ssio) Port Functional Overview
196
Ssio Port Signals and Registers
197
Ssio Operation
198
Ssio Handshaking
201
SSIO Handshaking Configuration
201
SSIO Handshaking Operation
202
Programming the Ssio Port
204
Configuring the SSIO Port Pins
204
Programming the Baud Rate and Enabling the Baud-Rate Generator
204
Controlling the Communications Mode and Handshaking
206
Enabling the SSIO Interrupts
208
Determining SSIO Port Status
208
Programming Considerations
208
Programming Example
210
Slave Port
212
Slave Port Functional Overview
215
Slave Port Signals and Registers
215
Hardware Connections
219
Slave Port Modes
221
Standard Slave Mode Example
221
Master Device Program
221
Slave Device Program
222
Demultiplexed Bus Timings
223
Shared Memory Mode Example
224
Master Device Program
224
Slave Device Program
225
Multiplexed Bus Timings
226
Configuring the Slave Port
227
Enabling the Slave Port Interrupts
229
Determining Slave Port Status
229
Using Status Bits to Synchronize Master and Slave
229
Event Processor Array (Epa)
232
Epa Functional Overview
234
Epa and Timer/Counter Signals and Registers
235
Timer/Counter Functional Overview
239
Cascade Mode (Timer 2 Only)
240
Quadrature Clocking Mode
240
Epa Channel Functional Overview
242
Operating in Capture Mode
244
Handling EPA Overruns
245
Operating in Compare Mode
246
Generating a Low-Speed PWM Output
247
Generating a Medium-Speed PWM Output
248
Generating a High-Speed PWM Output
249
Generating the Highest-Speed PWM Output
249
Programming the Epa and Timer/Counters
250
Configuring the EPA and Timer/Counter Port Pins
250
Programming the Timers
250
Programming the Capture/Compare Channels
253
Programming the Compare-Only Channels
258
Enabling the Epa Interrupts
259
Determining Event Status
260
Servicing the Multiplexed Epa Interrupt with Software
262
Using the TIJMP Instruction to Reduce Interrupt Service Overhead
264
Programming Examples for Epa Channels
266
EPA Compare Event Program
266
EPA Capture Event Program
267
EPA PWM Output Program
268
Analog-To-Digital Converter
270
A/D Converter Functional Overview
272
A/D Converter Signals and Registers
273
A/D Converter Operation
274
Programming the A/D Converter
275
Programming the A/D Test Register
276
Programming the A/D Result Register (for Threshold Detection Only)
277
Programming the A/D Time Register
277
Programming the A/D Command Register
279
Enabling the A/D Interrupt
280
Determining A/D Status and Conversion Results
280
Design Considerations
281
Designing External Interface Circuitry
282
Minimizing the Effect of High Input Source Resistance
283
Suggested A/D Input Circuit
284
Analog Ground and Reference Voltages
284
Using Mixed Analog and Digital Inputs
285
Understanding A/D Conversion Errors
285
Minimum Hardware Considerations
292
Minimum Connections
294
Unused Inputs
295
I/O Port Pin Connections
295
Applying and Removing Power
297
Noise Protection Tips
297
Providing the Clock
298
Using the On-Chip Oscillator
298
Using a Ceramic Resonator Instead of a Crystal Oscillator
300
Providing an External Clock Source
300
Resetting the Device
301
Generating an External Reset
303
Issuing the Reset (RST) Instruction
305
Issuing an Illegal IDLPD Key Operand
305
Enabling the Watchdog Timer
305
Detecting Oscillator Failure
305
Special Operating Modes
306
Special Operating Mode Signals and Registers
308
Reducing Power Consumption
310
Idle Mode
310
Powerdown Mode
311
Enabling and Disabling Powerdown Mode
311
Entering Powerdown Mode
312
Exiting Powerdown Mode
312
Generating a Hardware Reset
313
Asserting the External Interrupt Signal
313
Once Mode
316
Entering and Exiting ONCE Mode
316
Reserved Test Modes
316
Interfacing with External Memory
318
Internal and External Addresses
320
External Memory Interface Signals
321
Chip Configuration Registers and Chip Configuration Bytes
324
Bus Width and Multiplexing
329
Timing Requirements for BUSWIDTH
331
16-Bit Bus Timings
332
8-Bit Bus Timings
334
Wait States (Ready Control)
336
Bus-Hold Protocol
338
Enabling the Bus-Hold Protocol
340
Disabling the Bus-Hold Protocol
341
Hold Latency
341
Regaining Bus Control
341
Bus-Control Modes
342
Standard Bus-Control Mode
342
Write Strobe Mode
346
Address Valid Strobe Mode
348
Address Valid with Write Strobe Mode
352
Bus Timing Modes
353
Mode 3, Standard Mode
355
Mode 0, Standard Timing with One Automatic Wait State
355
Mode 1, Long Read/Write Mode
355
Mode 2, Long Read/Write with Early Address
356
Design Considerations
358
System Bus Ac Timing Specifications
358
Programming the Nonvolatile Memory
362
Programming Methods
364
Otprom Memory Map
365
Security Features
366
Controlling Access to Internal Memory
366
Controlling Access to the OTPROM During Normal Operation
367
Controlling Access to the OTPROM During Programming Modes
367
Controlling Fetches from External Memory
369
Enabling the Oscillator Failure Detection Circuitry
370
Programming Pulse Width
371
Modified Quick-Pulse Algorithm
372
Programming Mode Pins
374
Entering Programming Modes
376
Selecting the Programming Mode
376
Power-Up and Power-Down Sequences
377
Power-Up Sequence
377
Power-Down Sequence
377
Slave Programming Mode
378
Reading the Signature Word and Programming Voltages
378
Slave Programming Circuit and Memory Map
379
Operating Environment
380
Slave Programming Routines
382
Timing Mnemonics
387
Auto Programming Mode
388
Auto Programming Circuit and Memory Map
388
Operating Environment
390
Auto Programming Routine
390
Auto Programming Procedure
392
ROM-Dump Mode
393
Serial Port Programming Mode
394
Serial Port Programming Circuit and Memory Map
394
Changing Serial Port Programming Defaults
396
Executing Programs from Internal RAM
397
Reduced Instruction Set Monitor (RISM)
397
RISM Command Descriptions
398
RISM Command Examples
400
Example 1 - Programming the PPW
400
Example 2 - Reading OTPROM Contents
401
Example 3 - Loading a Program into Internal Code RAM
402
Example 4 - Setting the PC and Executing the Program
404
Writing to OTPROM with Examples 3 and 4
405
Run-Time Programming
406

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Intel 8XC196NT User Manual (597 pages)

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