Intel 8XC196K Series User Manual page 509

8XC196K x , J x , CA USER'S MANUAL
B.3 SIGNAL DESCRIPTIONS
Table B-5 defines the columns used in Table B-6, which describes the signals.
Column Heading
Name
Type
Description
Name Type
ACH7:0 (K x ) I
ACH7:2
(CA/J x )
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B-8
Table B-5. Description of Columns of Table B-6
Lists the signals, arranged alphabetically. Many pins have two functions, so
there are more entries in this column than there are pins. Every signal is
listed in this column.
Identifies the pin function listed in the Name column as an input (I), output
(O), bidirectional (I/O), power (PWR), or ground (GND).
Note that all inputs except RESET# are sampled inputs . RESET# is a level-
sensitive input. During powerdown mode, the powerdown circuitry uses
EXTINT as a level-sensitive input.
Briefly describes the function of the pin for the specific signal listed in the
Name column. Also lists the alternate fuction that are multiplexed with the
signal (if applicable).
Table B-6. Signal Descriptions
Analog Channels
These pins are analog inputs to the A/D converter.
These pins may individually be used as analog inputs (ACH x ) or digital inputs
(P0. x ). While it is possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading port 0 while a
conversion is in process can produce unreliable conversion results.
The ANGND and V
REF
to function.
NOTE: On the 8XC196J x and 87C196CA, ACH0 and ACH1 are tied to V
internally. The result of reading these channels is 3FFH (full-scale).
On the 8XC196K x, ACH7:0 are multiplexed as follows: ACH0/P0.0, ACH1/P0.1,
ACH2/P0.2, ACH3/P0.3, ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1,
ACH6/P0.6/PMODE.2, and ACH7/P0.7/PMODE.3.
On the 8XC196J x and 87C196CA, ACH7:2 are multiplexed as follows:
ACH2/P0.2, ACH3/P0.3, ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1,
ACH6/P0.6/PMODE.2, and ACH7/P0.7/PMODE.3.
ACH1:0 are not implemented on the 8XC196J x and 87C196CA.
Description
Description
pins must be connected for the A/D converter and port 0
REF