Serial Port Modes; Synchronous Mode (Mode 0) - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
Table 7-2. Serial Port Control and Status Registers (Continued)
Mnemonic Address
SP_BAUD 1FBCH,1FBDH Serial Port Baud Rate
SP_CON
SP_STATUS
†
Except as otherwise noted, write zeros to the reserved bits in these registers.
††
The T1CLK pin is not implemented on the 8XC196CA, JQ, JR, JT, JV devices. XTAL1 must provide the
serial port clock.
7.3

SERIAL PORT MODES

The serial port has both synchronous and asynchronous operating modes for transmission and re-
ception. This section describes the operation of each mode.
7.3.1

Synchronous Mode (Mode 0)

The most common use of mode 0, the synchronous mode, is to expand the I/O capability of the
device with shift registers (see Figure 7-2). In this mode, the TXD pin outputs a set of eight clock
pulses, while the RXD pin either transmits or receives data. Data is transferred eight bits at a time
with the least-significant bit first. Figure 7-3 shows a diagram of the relative timing of these sig-
nals. Note that only mode 0 uses RXD as an open-drain output.
In mode 0, RXD must be enabled for receptions and disabled for transmissions. (See "Program-
ming the Control Register" on page 7-8.) When RXD is enabled, either a rising edge on the RXD
input or clearing the receive interrupt (RI) flag in SP_STATUS starts a reception. When RXD is
disabled, writing to SBUF_TX starts a transmission.
Disabling RXD stops a reception in progress and inhibits further receptions. To avoid a partial or
undesired complete reception, disable RXD before clearing the RI flag in SP_STATUS. This can
be handled in an interrupt environment by using software flags or in straight-line code by using
the interrupt pending register to signal the completion of a reception.
7-4
This register selects the serial port baud rate and clock source. The
most-significant bit selects the clock source. The lower 15 bits
represent the BAUD_VALUE, an unsigned integer that determines
the baud rate.
1FBBH Serial Port Control
This register selects the communications mode and enables or
disables the receiver, parity checking, and ninth-bit data transmis-
sions. The TB8 bit is cleared after each transmission.
1FB9H Serial Port Status
This register contains the serial port status bits. It has status bits for
receive overrun errors (OE), transmit buffer empty (TXE), framing
errors (FE), transmit interrupt (TI), receive interrupt (RI), and
received parity error (RPE) or received bit 8 (RB8). Reading
SP_STATUS clears all bits except TXE; writing a byte to SBUF_TX
clears the TXE bit.
†
Description