Intel 8XC196K Series User Manual page 515

8XC196K x , J x , CA USER'S MANUAL
Name Type
P2.7:0 (K x ) I/O
P2.7:6, P2.4,
P2.2:0 (J x , CA)
P3.7:0 I/O
P4.7:0 I/O
P5.7:0 I/O
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B-14
Table B-6. Signal Descriptions (Continued)
Port 2
This is a standard bidirectional port that is multiplexed with individually
selectable special-function signals.
P2.6 is multiplexed with the ONCE# function (CA, JR, JT, JV, KS, KT) or a
special test-mode-entry function (KR, KQ). If this pin is held low during reset,
the device will enter ONCE mode or a reserved test mode, so exercise caution
if you use this pin for input. If you choose to configure this pin as an input,
always hold it high during reset and ensure that your system meets the V
specification (see datasheet) to prevent inadvertent entry into ONCE mode or a
test mode.
On the 8XC196K x , port 2 is multiplexed as follows: P2.0/TXD/PVER,
P2.1/RXD/PALE#, P2.2/EXTINT/PROG#, P2.3/BREQ#,
P2.4/INTOUT#/AINC#, P2.5/HOLD#, P2.6/HLDA#/ONCE#(KT, KS)/CPVER,
P2.7/CLKOUT/PACT#.
On the 8XC196J x and 87C196CA, port 2 is multiplexed as follows:
P2.0/TXD/PVER, P2.1/RXD/PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#,
P2.6/ONCE#/CPVER, P2.7/CLKOUT/PACT#. P2.3 and P2.5 are not imple-
mented.
Port 3
This is an 8-bit, bidirectional, memory-mapped I/O port with open-drain outputs.
The pins are shared with the multiplexed address/data bus, which has comple-
mentary drivers.
P3.7:0 are multiplexed with AD7:0, SLP7:0 (K x only), and PBUS.7:0.
Port 4
This is an 8-bit, bidirectional, memory-mapped I/O port with open-drain outputs.
P4.7:0 are multiplexed with AD15:8 and PBUS15:8.
Port 5
This is an 8-bit, bidirectional, memory-mapped I/O port.
P5.4 is multiplexed with the ONCE# function (KR, KQ) or a special test-mode-
entry function (CA, KS, KT). If this pin is held low during reset, the device will
enter ONCE mode or a reserved test mode, so exercise caution if you use this
pin for input. If you choose to configure this pin as an input, always hold it high
during reset and ensure that your system meets the V
datasheet) to prevent inadvertent entry into ONCE mode or a test mode.
On the 8XC196K x , port 5 is multiplexed as follows: P5.0/ALE/ADV#/SLPALE,
P5.1/INST/SLPCS#, P5.2/WR#/WRL#/SLPWR#, P5.3/RD#/SLPRD#,
P5.4/ONCE# (KR, KQ)/SLPINT, P5.5/BHE#/WRH#, P5.6/READY, and
P5.7/BUSWIDTH.
On the 8XC196J x , port 5 is multiplexed as follows: P5.0/ADV#/ALE,
P5.2/WR#/WRL#, and P5.3/RD#. P5.1 and P5.7:4 are not implemented.
On the 87C196CA, port 5 is multiplexed as follows: P5.0/ADV#/ALE,
P5.2/WR#/WRL#, P5.3/RD#, P5.5/BHE#/WRH#, and P5.6/READY. P5.4 is not
multiplexed; P5.1 and P5.7 are not implemented.
Description
specification (see
IH
IH