Intel 8XC196K Series User Manual page 229

Table of Contents

8XC196K x , J x , CA USER'S MANUAL

Each EPA channel has a control register, EPAx_CON (capture/compare channels) or

COMPx_CON (compare-only channels); an event-time register, EPAx_TIME (capture/compare

channels) or COMPx_TIME (compare-only channels); and a timer input (Figure 10-5). The con-

trol register selects the timer, the mode, and either the event to be captured or the event that is to

occur. The event-time register holds the captured timer value in capture mode and the event time

in compare mode. See "Programming the Capture/Compare Channels" on page 10-20 and "Pro-

gramming the Compare-only Channels" on page 10-25 for configuration information.

The two compare-only channels share output pins with capture/compare channels 8 and 9. This

means that both capture/compare channel 8 and compare-only channel 0 can set, clear, or toggle

the EPA8/COMP0 pin. They can operate at the same time, and neither has priority in its access to

the output pin. Capture/compare channel 9 and compare-only channel 1 share the EPA9/COMP1

pin in this same way.

TIMER1 overflow

† EPA1 and 3 only. If enabled for EPA1, EPA0 shares the EPA1 pin. If enabled for EPA3, EPA2

shares the EPA3 pin.

Figure 10-5. A Single EPA Capture/Compare Channel

Timer/Counter Unit

Capture Overrun

Mode Control

External clocking (T x CLK) with up to 6-bit prescaler

Quadrature clocking through T x CLK and T x DIR

Internal clocking with up to 6-bit prescaler

EPA Capture/Compare

Mode Selection