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INTERFACING WITH EXTERNAL MEMORY
The device can interface with a variety of external memory devices. It supports either a fixed 8-
bit bus width, a fixed 16-bit bus width, or a dynamic 8-bit/16-bit bus width; internal control of
wait states for slow external memory devices; a bus-hold protocol that enables external devices
to take over the bus; and several bus-control modes. These features provide a great deal of flexi-
bility when interfacing with external memory devices.
In addition to describing the signals and registers related to external memory, this chapter discuss-
es the process of fetching the chip configuration bytes and configuring the external bus. It also
provides examples of external memory configurations.
15.1 EXTERNAL MEMORY INTERFACE SIGNALS
Table 15-1 describes the external memory interface signals. For some signals, the pin has an al-
ternate function (shown in the Multiplexed With column). In some cases the alternate function is
a port signal (e.g., P2.7). Chapter 6, "I/O Ports," describes how to configure a pin for its I/O port
function and for its special function. In other cases, the signal description includes instructions
for selecting the alternate function.
Function
Type
Name
AD15:0
I/O
Address/Data Lines
These pins provide a multiplexed address and data bus. During the
address phase of the bus cycle, address bits 0–15 are presented on
the bus and can be latched using ALE or ADV#. During the data
phase, 8- or 16-bit data is transferred. When a bus access is not
occurring, these pins revert to their I/O port function.
ADV#
O
Address Valid
This active-low output signal is asserted only during external
memory accesses. ADV# indicates that valid address information is
available on the system address/data bus. The signal remains low
while a valid bus cycle is in progress and is returned high as soon as
the bus cycle completes.
An external latch can use this signal to demultiplex the address from
the address/data bus. A decoder can also use this signal to generate
chip selects for external memory.
Table 15-1. External Memory Interface Signals
Description
CHAPTER 15
Multiplexed
With
P4.7:0
P3.7:0
ALE/P5.0
15-1
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