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Intel Agilex User Manual

Logic array blocks and adaptive logic modules
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Intel
Agilex
Logic Array Blocks
and Adaptive Logic Modules User
Guide
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UG-20204 | 2019.04.02
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Summary of Contents for Intel Agilex

  • Page 1 ® ™ Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide Subscribe UG-20204 | 2019.04.02 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    3.1.4. LAB Control Signals..................8 3.2. ALM........................9 3.2.1. ALM Resources..................9 3.2.2. ALM Output.....................10 3.2.3. ALM Operating Modes................11 4. Document Revision History for the Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide..................20 ® ™ Intel...

  • Page 3: Intel ® Agilex ™ Lab And Alm Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 4: Intel Hyperflex ™ Register

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Intel Agilex Lab And Alm Architecture And Features

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 6: Mlab

    3. Intel Agilex LAB and ALM Architecture and Features UG-20204 | 2019.04.02 Related Information MLAB on page 6 3.1.1. MLAB Each MLAB supports a maximum of 640 bits of simple dual-port SRAM. You can configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in a configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.

  • Page 7: Carry Chain Interconnects

    Outputs 3.1.3. Carry Chain Interconnects There is a dedicated carry chain path between the ALMs. Intel Agilex devices include an enhanced interconnect structure in LABs for routing carry chains for efficient arithmetic functions. These ALM-to-ALM connections bypass the local interconnect.

  • Page 8: Lab Control Signals

    A low skew clock network distributes global signals to the row clocks [5..0]. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for routing efficiency. The Intel Quartus Prime Compiler automatically routes critical design paths on faster interconnects to improve design performance and optimizes the device resources.

  • Page 9: Alm

    3. Intel Agilex LAB and ALM Architecture and Features UG-20204 | 2019.04.02 Intel Agilex devices provide a device-wide reset pin ( ) that resets all the DEV_CLRn registers in the device. You can enable the pin in the Intel Quartus Prime DEV_CLRn software before compilation.

  • Page 10: Alm Output

    ALM. The ALM can also drive out registered and unregistered versions of the LUT or adder output. The following figure shows the Intel Agilex ALM connectivity. In the Intel Quartus Prime Resource Property Editor, the entire ALM connection is simplified. Some routings will be routed internally by the Intel Quartus Prime software.

  • Page 11: Alm Operating Modes

    Arithmetic mode 3.2.3.1. Normal Mode Normal mode allows two functions to be implemented in one Intel Agilex ALM, or a single function of up to six inputs. Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
  • Page 12 ALMs by the Intel Quartus Prime software to achieve the best possible performance. As a device begins to fill up, the Intel Quartus Prime software automatically uses the full potential of the Intel Agilex ALM. The Intel Quartus Prime Compiler automatically searches for functions using common inputs or completely ®...
  • Page 13 3. Intel Agilex LAB and ALM Architecture and Features UG-20204 | 2019.04.02 independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource use by setting location assignments. Figure 9.
  • Page 14 3. Intel Agilex LAB and ALM Architecture and Features UG-20204 | 2019.04.02 Figure 10. 3-Input LUT Mode Function in Normal Mode are available for register packing. dataa datab labclk labclk_phi1 reg0 dataa datae reg1 3-Input LUT datad0 datac0 To General...
  • Page 15 LUT and directly feed into the register, depending on the packed register mode used. For Intel Agilex devices, the following types of packed register modes are supported: • 5-input LUT with 1 packed register path •...
  • Page 16 The clear and clock enable options are LAB-wide signals that affect all registers in the LAB. You can individually disable or enable these signals for each pair of registers in an adaptive LUT (ALUT). The Intel Quartus Prime software automatically places any registers that are not used by the counter into other LABs.
  • Page 17 3.2.3.4. Time Borrowing and Latch Modes In Intel Agilex devices, you can choose to use the registers in normal mode, time borrowing mode, or latch mode depending on the selection of the LAB clocks ). There are a total of four...
  • Page 18 3. Intel Agilex LAB and ALM Architecture and Features UG-20204 | 2019.04.02 Within the four LABCLKs being generated, two out of the four s are normal LABCLK , while the remaining two are the delayed clocks ( LABCLK LABCLK LABCLK_Phi1...
  • Page 19 1. Add slave latch to CE feedback (CE_FB) path, holds previous state during transparency window. Besides the time-borrowing mode, the Intel Agilex devices also support latch mode in the ALM register, by controlling the in the LAB control block. During the latch LABCLK mode, only one clock is available for the master and slave latch per LAB, respectively.

  • Page 20: Document Revision History For The Intel Agilex Logic Array Blocks And Adaptive Logic Modules User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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