Design Considerations; Hardware Reset; Software Initialization; Bus-Off State - Intel 8XC196K Series User Manual

Table of Contents

12.9 DESIGN CONSIDERATIONS

This section outlines design considerations for the CAN controller.

A hardware reset clears the error management counters and the bus-off state and leaves the reg-

isters with the values listed in Table 12-14.

Standard Global Mask

Extended Global Mask

Message 15 Mask

Bit Timing 0

Bit Timing 1

Message Object x

The software initialization state allows software to configure the CAN controller's RAM without

risk of messages being received or transmitted during this time. Setting the INIT bit in the control

set or a software write can set the INIT bit. While INIT is set, all message transfers to and from

the CAN controller are stopped and the error counters and bit timing registers are unchanged.

Your software should clear the INIT bit to cause the CAN controller to exit the software initial-

ization state. At this time, the CAN controller synchronizes itself to the CAN bus by waiting for

a bus idle state (11 consecutive recessive bits) before participating in bus activities.

If an error counter reaches 256, the CAN controller isolates itself from the CAN bus, sets the

BUSOFF bit in the status register, and sets the INIT bit in the control register. While INIT is set,

all message transfers to and from the CAN controller are stopped; the error counters and bit tim-

ing registers are unchanged. Software must clear the INIT bit to initiate the bus-off recovery se-

CAN SERIAL COMMUNICATIONS CONTROLLER

Table 12-14. Register Values Following Reset

1E x 0–1E x E

unchanged (undefined at power-up)

unchanged (undefined at power-up)