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8XC196K x , J x , CA USER'S MANUAL
4.1.4.1
Reserved Memory Locations
Several memory locations are reserved for testing or for use in future products. Do not read or
write these locations except to initialize them. The function or contents of these locations may
change in future revisions; software that uses reserved locations may not function properly. Al-
ways initialize reserved locations to the values listed in Table 4-2 on page 4-3.
4.1.4.2
Interrupt and PTS Vectors
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. The
peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks. See
Chapter 5, "Standard and PTS Interrupts," for more information on interrupt and PTS vectors.
4.1.4.3
Security Key
The security key prevents unauthorized programming access to the nonvolatile memory. See
Chapter 16, "Programming the Nonvolatile Memory," for details.
4.1.4.4
Chip Configuration Bytes (CCBs)
The chip configuration bytes (CCBs) specify the operating environment. They specify the bus
width, bus-control mode, and wait states. They also control powerdown mode, the watchdog tim-
er, and nonvolatile memory protection.
The CCBs are the first bytes fetched from memory when the device leaves the reset state. The
post-reset sequence loads the CCBs into the chip configuration registers (CCRs). Once they are
loaded, the CCRs cannot be changed until the next device reset. Typically, the CCBs are pro-
grammed once when the user program is compiled and are not redefined during normal operation.
"Chip Configuration Registers and Chip Configuration Bytes" on page 15-4 describes the CCBs
and CCRs.
For devices with user-programmable nonvolatile memory, the CCBs are loaded for normal oper-
ation, but the PCCBs are loaded into the CCRs if the device is entering programming modes. See
Chapter 16, "Programming the Nonvolatile Memory," for details.
4-4
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