Intel 8XC196K Series User Manual page 576

Table of Contents

When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending

(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.

Software can generate an interrupt by setting the corresponding interrupt pending bit.

When set, this bit indicates that the corresponding interrupt is pending. The interrupt bit is

cleared when processing transfers to the corresponding interrupt vector.

The standard interrupt vector locations are as follows:

Bit Mnemonic Interrupt

All CAN-controller interrupts are multiplexed into the single CAN interrupt input

(INT13). The interrupt service routine associated with INT13 must read the CAN interrupt

pending register (CAN_INT) to determine the source of the interrupt request.

Bit 7 is reserved on the 8XC196J x devices, bit 5 is reserved on the 8XC196J x , K x devices, and bit 0

is reserved on the 87C196CA, 8XC196J x devices. For compatibility with future devices, always write

zeros to these bits.

Nonmaskable Interrupt

CAN Peripheral

SIO Transmit

SSIO 1 Transfer

SSIO 0 Transfer

Slave Port Command Buffer Full

Reset State:

Standard Vector