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CCR1
The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode.
Two of its bits combine with three bits of CCR0 to control wait states and bus width.
7
CA, J x , KQ, KR
1
7
KS, KT
MSEL1
Bit
Bit
Number
Mnemonic
7:6
1
(CA, J x , KQ,
KR)
MSEL1:0
(KS, KT)
5
0
4
1
3
WDE
2
BW1
Figure 15-2. Chip Configuration 1 (CCR1) Register
1
0
1
MSEL0
0
1
To guarantee device operation, write ones to these bits.
External Access Timing Mode Select
These bits control the bus-timing modes.
MSEL1
MSEL0
0
0
standard mode plus one wait state
0
1
long read/write
1
0
long read/write with early address
1
1
standard mode
To guarantee device operation, write zero to this bit.
To guarantee device operation, write one to this bit.
Watchdog Timer Enable
Selects whether the watchdog timer is always enabled or enabled the first
time it is cleared.
1 = enabled first time it is cleared
0 = always enabled
Buswidth Control
This bit, along with the BW0 bit (CCR0.1), selects the bus width.
BW1 BW0
0
0
illegal
0
1
16-bit only
1
0
8-bit only
1
1
BUSWIDTH pin controlled
†
This mode is unavailable on the 87C196CA, 8XC196J x devices. The
BUSWIDTH pin is not implemented.
INTERFACING WITH EXTERNAL MEMORY
Address:
Reset State:
WDE
BW1
WDE
BW1
Function
†
201AH
XXH
0
IRC2
0
0
IRC2
0
15-7
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