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CAN_BTIME1
(87C196CA)
Program the CAN bit timing 1 (CAN_BTIME1) register to define the sample time and the sample
mode. The CAN controller samples the bus during the last one (in single-sample mode) or three (in
three-sample mode) time quanta of t
Therefore, specifying the lengths of t
mission point.
7
87C196CA
SPL
Bit
Bit
Number
Mnemonic
3:0
TSEG1
NOTES:
1.
The CCE bit (CAN_CON.6) must be set to enable write access to this register.
2.
For correct operation according to the CAN protocol, the total bit time must be at least 8 time
quanta, so the sum of the programmed values of TSEG1 and TSEG2 must be at least 5. (The
total bit time is the sum of t
and the hardware adds 1 to both TSEG1 and TSEG2. Therefore, if TSEG1 + TSEG2 = 5, the
total bit length will be equal to 8 (1+5+1+1)). Table 12-11 lists additional conditions that must be
met to maintain synchronization.
Figure 12-8. CAN Bit Timing 1 (CAN_BTIME1) Register (Continued)
Table 12-11. Bit Timing Requirements for Synchronization
Bit Time
Requirement
Segment
≥ 3tq
≥ t
t
+ t
1
TSEG
SJW
PROP
≥ t
+ t
SJW
PROP
≥ 2tq
t
2
TSEG
≥ t
SJW
CAN SERIAL COMMUNICATIONS CONTROLLER
, and initiates a transmission at the end of t
1
TSEG
and t
1
TSEG
TSEG
TSEG2.2
TSEG2.1
TSEG2.0
Time Segment 1
This field defines the length of time that precedes the sample point within a
bit time. Valid programmed values are 2–15; the hardware adds 1 to this
value. In three-sample mode, the hardware adds 2 time quanta to allow
time for the two additional samples. (Note 2)
+ t
_
1
SYNC
SEG
TSEG
minimum tolerance with 1tq propagation delay allowance
for single-sample mode
+ 2tq for three-sample mode
minimum tolerance
if t
> t
, sampling may occur after the bit time
2
SJW
TSEG
Reset State:
defines both the sample point and the trans-
2
TSEG1.3
TSEG1.2
Function
+ t
. The length of t
2
TSEG
SYNC
Comments
Address:
1E4FH
Unchanged
.
2
TSEG
0
TSEG1.1
TSEG1.0
is 1 time quanta,
_
SEG
12-17
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