Intel 8XC196K Series User Manual page 410

CCR1, CCR0
The chip configuration registers (CCRs) control bus-control signals, bus width, wait states, powerdown
mode, and internal memory protection. These registers are loaded from the PCCBs during
programming modes and from the CCBs for normal operation.
7
MSEL1 MSEL0
7
LOC1 LOC0
Bit Mnemonic
†
MSEL1:0
WDE
BW1
IRC2
LOC1:0
IRC1:0
ALE
WR
BW0
PD
†
These bits are reserved on the 8XC196CA, J x, KQ, KR. They are unique to the 8XC196KS and KT.
Figure 16-6. Chip Configuration Registers (CCRs)
PROGRAMMING THE NONVOLATILE MEMORY
— —
IRC1 IRC0
External Access Timing Mode Select
PCCB default is standard mode.
Watchdog Timer Enable
PCCB default is initially disabled (enabled the first time WDT is cleared).
Buswidth Control
For the K x , PCCB default selects BUSWIDTH pin control.
For the CA, J x , the PCCB default selects a16-bit bus.
Internal Ready Control.
For the K x , PCCB default selects READY pin control.
For the CA, J x , the PCCB default selects zero wait states.
Security Bits
PCCB default selects no protection.
Internal Ready Control
For the K x , PCCB default selects READY pin control.
For the CA, J x , the PCCB default selects zero wait states.
Select Address Valid Strobe Mode.
PCCB default selects ALE.
Select Write Strobe Mode.
For the K x , PCCB default selects WR# and BHE#.
For the CA, J x , the PCCB default selects WR# (BHE# is not imple-
mented).
Buswidth Control
For the K x , PCCB default selects BUSWIDTH pin control.
For the CA, J x , the PCCB default selects a16-bit bus.
Powerdown Enable.
PCCB default enables powerdown.
Address:
Reset State: from CCBs XXH, XXH
Reset State:
WDE BW1
ALE WR
Function
201AH, 2018H
see bit descriptions
0
IRC2 —
0
BW0 PD
16-19