Enabling The Ssio Interrupts; Determining Ssio Port Status; Programming Considerations - Intel 8XC196K Series User Manual

8.5.4

Enabling the SSIO Interrupts

Each SSIO channel can generate an interrupt request if you enable the individual interrupt as well
as globally enabling servicing of all maskable interrupts. The INT_MASK1 register enables and
disables individual interrupts. To enable an SSIO interrupt, set the corresponding bit in
INT_MASK1 (see Table 8-2 on page 8-2) and execute the EI instruction to globally enable inter-
rupt servicing. See Chapter 5, "Standard and PTS Interrupts," for more information about inter-
rupts.
8.5.5

Determining SSIO Port Status

The SSIO_BAUD register (Figure 8-5 on page 8-10) indicates the current status and value of the
down-counter. The SSIOx_CON register (Figure 8-6) indicates whether an underflow or over-
flow has occurred and whether the channel is ready to transmit or receive. Read the INT_PEND1
register (see Table 8-2 on page 8-2) to determine the status of SSIO interrupts. See Chapter 5,
"Standard and PTS Interrupts," for details about interrupts.
8.6

PROGRAMMING CONSIDERATIONS

For transmissions, the time that you write to SSIOx_BUF determines the data setup time (the
length of time between data being placed on the data pin and the first clock edge on the clock pin).
The reason for this anomaly is that the baud-rate down-counter starts when you write to
SSIO_BAUD, but the transmission doesn't start until you write to SSIOx_BUF. The write to
SSIOx_BUF can occur at any point during the count. Since the most-significant bit (MSB)
doesn't change until the falling edge of SCx (which is triggered by a counter overflow), the width
of the MSB appears to vary (Figure 8-7). If you write to SSIOx_BUF early in the count, the MSB
seems relatively long. If you write to SSIOx_BUF late in the count, the MSB seems relatively
short.
For example, assume that you write 93H to SSIO_BAUD (the MSB enables the baud-rate gener-
ator, and the lower seven bits define the initial count value). As soon as this register is written,
the down-counter starts decrementing from 13H. If the counter is at 11H when you write to
SSIOx_BUF, the MSB will remain on the data pin for approximately 8.5 µs. If the counter is at
03H when you write to SSIOx_BUF, the MSB will remain on the data pin for only approximately
1.5 µs.
SYNCHRONOUS SERIAL I/O (SSIO) PORT
8-13