Determining Event Status - Intel 8XC196K Series User Manual

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8XC196K x , J x , CA USER'S MANUAL

10.7 DETERMINING EVENT STATUS

In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event

(even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt

pending bit is set each time a programmed event is captured and the event time moves from the

capture buffer to the EPAx_TIME register. If the capture buffer is full when an event occurs, an

overrun interrupt pending bit is set.

The EPA0–EPA3 pending bits are located in INT_PEND (Figure 5-5 on page 5-13). The pending

bits for the multiplexed interrupts (those that share EPAx) are located in EPA_PEND (Figure

10-14) and EPA_PEND1 (Figure 10-15). If an interrupt is masked, software can still poll the in-

terrupt pending registers to determine whether an event has occurred.

When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt

pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that

identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA

interrupt pending bit associated with the EPAIPV priority value is cleared.

Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is

cleared when the EPA interrupt priority vector register (EPAIPV) is read.

Bits 2–5 and 12–15 are reserved on the 8XC196CA, J x devices. For compatibility with future

devices, write zeros to these bits.

Figure 10-14. EPA Interrupt Pending (EPA_PEND) Register

Reset State: