Situations That Increase Interrupt Latency - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit
and forces a call to the address contained in the corresponding interrupt vector after completing
the current instruction. The procedure that gets the vector and forces the call requires 11 state
times. If the stack is in external RAM, the call requires an additional two state times assuming a
zero-wait-state bus.
When a PTS interrupt request is acknowledged, it immediately vectors to the PTSCB and begins
executing the PTS routine.
5.4.1

Situations that Increase Interrupt Latency

If an interrupt request occurs while any of the following instructions are executing, the interrupt
will not be acknowledged until after the next instruction is executed:
•
the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions
•
any of these eight protected instructions: DI, EI, DPTS, EPTS, POPA, POPF, PUSHA,
PUSHF (see Appendix A for descriptions of these instructions)
•
any of the read-modify-write instructions: AND, ANDB, OR, ORB, XOR, XORB
Both the unimplemented opcode interrupt and the software trap interrupt prevent other interrupt
requests from being acknowledged until after the next instruction is executed.
Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS re-
sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer
of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume
a block transfer of 32 words from one external memory location to another. See Table 5-4 on page
5-10 for PTS cycle execution times.
5-8