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Intel MCS 51 User Manual
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Table Of Contents
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Contents
Table of Contents
Bookmarks
Table of Contents
Contents
Table of Contents
Architectural Overview
Introduction
Block Diagram
Program Memo
CHMOS Devices
Logical Separation of Program and Data Memory
Data Memory
Program Memory
SFR Space
The Mc951 Instruction Set
Program Status Word
Direct Addressing
Register Instructions
Addressing Modes
Arithmetic Instructions
Logical Instructions
Data Transfers
Internal RAM
External RAM
Lookup Tables
Boolean Instructions
Relative Offset
Jump
Using an External Clock
Using the on Chip Oscillator
CPU Timing
State Sequences
Machine Cycles
Interrupt Enables
Interrupt Priorities
Interrupt Structure
Simulating a Third Priority Level in Software
Additional References
Memory Organization
Program Memory
Data Memory
Direct and Indirect Address Area
Special Function Registers
What Do the Sfrs Contain Just
Sfr Memory Map
Not Bit Addressable
Psw: Program Status Word. Bit Addressable
Interrupts
Assigning Higher Priority to One or more Interrupts
Bit Addressable
Priority Within Level
Addressable
Tcon: Timefvcounter Control Register. Bit Addressable
Timer/Counter Control Register
Timer Set-Up
Timer/Counter
T2Con: Timewcounter 2 Control Register. Bit Addressable
Generating Baud Rates
Scon: Serial Port Control Register Bit Addressable
Serial Port in Mode 1
Serial Port in Mode O
Serial Port Set-Up
Serial Port in Mode 3
Using Timer/Counter 1 to Generate Baud Rates
Flag Settings
Instruction Set Summary
Instruction Definitions
Hardware Description
Introduction
Specialfunctionregisters
Accumulator
B Register
Data Pointer
Stack Pointer
Port Structures and Operation
PSW Program Status Word Register
I/O Configurations
Writing to a Port
Port Loading and Interfacing
Accessing External Memory
Read-Modify-Write Feature
Timer Oand Timer 1
Timer2
Serial Interface
Multiprocessor Communications
Serial Port Control Register
Baud Rates
Scon
Using Timer 1 to Generator Baud Rates
Using Timer 2 to Generator Baud Rates
More about Mode 0
More about Mode 1
More about Modes 2 and 3
Interrupt Enable Register
How Interrupts Are Handled
Interrupt Response Timing Diagram
IP Interrupt Priority Register
Priority Level Structure
External Interrupts
Response Time
Reset
Reset Timing
Single-Step Operation
CHMOS Power Reduction Modes
Operatfon
Power-On Reset
Power-Saving Modes of
Idle and Power down Hardware
Idle Mode
Power Control Register
Power down Mode
Eprom Versions
Exposure to Light
One Lock Bit Scheme
Two Program Memory Lock Schemes
HMOS Versions
ONCE Mode
ROM Protection
The On-Chip Oscillators
ESR Vs Frequency
Using the HMOS On-Chip Oscillator
CHMOS Versions
Internal Timing
Using the CHMOS On-Chip Oscillator
External Data Memory Read Cycle
External Program Memory Fetches
External Data Memory Write Cycle
Port Operation
Datamemory
Pin Description
Special Function Registers
Serial Port Registers
Timer Registers
AUTO-RELOAD (up or down Counter)
Capture Mode
Timer 2 in Capture Mode
Baud Rate Generator
Automatic Address Recognitino
Framing Error Detection
Programmable Clock out
Uart
Interrupt Priority Structure
Interrupt Sources
Power down Mode
Power off Flag
Program Memory Lock
Additional References
ONCE Mode
Data Memory
Introduction
Program Memory
Special Function Registers
Port Structures and Operation
Writing to a Port
Accessing External Memory
Port Loading and Interfacing
Read-Modify-Write Feature
Timer Oand Timer 1
Timerwcounters
Timer 2
Auto Reload Mode
Counter
T2Mod
Timer 2 Auto Reload Mode
Baud Rate Generator Mode
Programmable Counter Array
PCA 16-Bit Timer/Counter
Cmod
Capture/Compare Modules
Ccon
PCA Module Modes
16-Bit Capture Mode
16-Bit Software Timer Mode
PCA 16-Bit Capture Mode
High Speed Output Mode
Watchdog Tmer Mode
PCA 8-Bit PWM Mode
Pulse Width Modulator Mode
Watchdog Timer Mode
Serial Interface
Automatic Address Recognition
Multiprocessor Communications
Baud Rates
Rates
Using Llmer 1 to Generate Baud
Using Timer 2 to Generate Baud
Interrupts
External Interrupts
Interrupt Enable
PCA Interrupt
Priority Level Structure
Serial Porl Interrupt
Timer Interrupts
Reset
Response Time
Operation
Power-On Reset
Power-Saving Modes of
87C51GB Hardware Description
Idlemode
Powerdownmode
Poweroff Flag
On-Chip Oscillator
Once Mode
Programmemorylock
Cpu Timing
Comparison of 80C152 and 80C51Bh Features
Memoryspace
Interruptstructure
Globalserialchannel
Introduction
Localserialchannel
Power Downand Idle
CSMA/CD Operation
SDLC Operation
Userdefinedprotocols
Usingthe GSC
Registerdescriptions
Dma Operation
DMA Withthe 80C152
Serial Backplanevs Network Environment
Hold/Holdacknowledge
Timingdiagrams
Dmaarbitration
Summaryof DMA Controlbits
Interruptstructure
GSC Transmittererror Conditions
GSC Receivererrorconditions
Glossary
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Program Memo
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MCS@51 MICROCONTROLLER
FAMILY USER'S MANUAL
ORDER
NO.: 272383-002
FEBRUARY
1994
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