Intel 8XC196K Series User Manual page 565

8XC196K x, J x , CA USER'S MANUAL
EPA_PEND
EPA_PEND
When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt
pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
15
CA, J x
—
7
OVR2
15
K x
EPA4
7
OVR2
Bit
Number
†
15:0 Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
†
Bits 2–5 and 12–15 are reserved on the 8XC196CA, J x devices. For compatibility with future
devices, write zeros to these bits.
C-38
— — —
OVR3 — —
EPA5 EPA6 EPA7
OVR3 OVR4 OVR5
Function
Address:
Reset State:
EPA8 EPA9 OVR0
— — OVR8
EPA8 EPA9 OVR0
OVR6 OVR7 OVR8
1FA2H
0000H
8
OVR1
0
OVR9
8
OVR1
0
OVR9