Intel 8XC196K Series User Manual page 563

8XC196K x, J x , CA USER'S MANUAL
EPA_MASK
EPA_MASK
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with
the multiplexed EPA x interrupt.
15
CA, Jx —
7
0VR2
15
K x EPA4
7
OVR2
Bit
Number
† Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
15:0
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the interrupt
mask register (INT_MASK.0 = 1).
†
Bits 2–5 and 12–15 are reserved on the 8XC196CA, J x devices. For compatibility with future
devices, write zeros to these bits.
C-36
— — —
OVR3 — —
EPA5 EPA6 EPA7
OVR3 OVR4 OVR5
Function
Address:
Reset State:
EPA8 EPA9 OVR0
— — OVR8
EPA8 EPA9 OVR0
OVR6 OVR7 OVR8
1FA0H
0000H
8
OVR1
0
OVR9
8
OVR1
0
OVR9