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Figure
8XC196K x Block Diagram ............................................................................................2-3
2-1
2-2
Block Diagram of the Core ...........................................................................................2-3
2-3
Clock Circuitry ..............................................................................................................2-7
2-4
Internal Clock Phases ..................................................................................................2-8
4-1
Register File Memory Map .........................................................................................4-11
4-2
Windowing ..................................................................................................................4-14
4-3
Window Selection Register (WSR).............................................................................4-15
5-1
Flow Diagram for PTS and Standard Interrupts ...........................................................5-2
5-2
Standard Interrupt Response Time ..............................................................................5-9
5-3
PTS Interrupt Response Time ....................................................................................5-10
5-4
PTS Select (PTSSEL) Register ..................................................................................5-12
5-5
Interrupt Mask (INT_MASK) Register.........................................................................5-13
5-6
Interrupt Mask 1 (INT_MASK1) Register....................................................................5-14
5-7
Interrupt Pending (INT_PEND) Register ....................................................................5-17
5-8
Interrupt Pending 1 (INT_PEND1) Register ...............................................................5-18
5-9
PTS Control Blocks ....................................................................................................5-19
5-10
PTS Service (PTSSRV) Register ...............................................................................5-20
5-11
PTS Mode Selection Bits (PTSCON Bits 7:5) ............................................................5-21
5-12
PTS Control Block – Single Transfer Mode................................................................5-22
5-13
PTS Control Block – Block Transfer Mode .................................................................5-25
5-14
PTS Control Block – A/D Scan Mode .........................................................................5-27
5-15
A Generic PWM Waveform ........................................................................................5-32
5-16
PTS Control Block – PWM Toggle Mode ...................................................................5-34
5-17
EPA and PTS Operations for the PWM Toggle Mode Example.................................5-36
5-18
PTS Control Block – PWM Remap Mode...................................................................5-39
5-19
EPA and PTS Operations for the PWM Remap Mode Example ................................5-41
6-1
Standard Input-only Port Structure ...............................................................................6-3
6-2
Bidirectional Port Structure...........................................................................................6-8
6-3
Address/Data Bus (Ports 3 and 4) Structure ..............................................................6-17
7-1
SIO Block Diagram .......................................................................................................7-1
7-2
Typical Shift Register Circuit for Mode 0 ......................................................................7-5
7-3
Mode 0 Timing..............................................................................................................7-5
7-4
Serial Port Frames for Mode 1 .....................................................................................7-6
7-5
Serial Port Frames in Mode 2 and 3.............................................................................7-7
7-6
Serial Port Control (SP_CON) Register........................................................................7-9
7-7
Serial Port Baud Rate (SP_BAUD) Register ..............................................................7-10
7-8
Serial Port Status (SP_STATUS) Register.................................................................7-13
8-1
SSIO Block Diagram ....................................................................................................8-1
8-2
SSIO Operating Modes ................................................................................................8-4
8-3
SSIO Transmit/Receive Timings ..................................................................................8-6
8-4
SSIO Handshaking Flow Diagram................................................................................8-7
8-5
Synchronous Serial Port Baud (SSIO_BAUD) Register .............................................8-10
8-6
Synchronous Serial Control x (SSIO x _CON) Registers .............................................8-11
8-7
Variable-width MSB in SSIO Transmissions ..............................................................8-14
FIGURES
CONTENTS
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