Intel 8XC196K Series User Manual page 389

8XC196K x , J x , CA USER'S MANUAL
Symbol
The 87C196CA, 8XC196J x , K x Meets These Specifications (Continued)
T AD15:8 Hold after WR# High
WHAX
Minimum time the high byte of the address in 8-bit mode will be valid after WR# inactive.
†
T BHE# , INST
WHBX
Minimum time these signals will be valid after WR# inactive. (8XC196K x only)
T WR# High to ALE/ADV# High
WHLH
Time between WR# going inactive and next ALE/ADV#. Also used to calculate WR# inactive
and next address valid.
T Data Hold after WR# High
WHQX
Length of time after WR# rises that the data stays valid on the bus. Memory devices must meet
this specification.
T WR# Low to WR# High
WLWH
WR# pulse width.
T XTAL1 High to CLKOUT High or Low
XHCH
†
8XC196K x only; the BUSWIDTH and BHE# pins are not implemented on the 87C196CA, 8XC196J x .
††
8XC196K x , 87C196CA only; the READY and INST pins are not implemented on the 8XC196J x .
15-40
Table 15-8. AC Timing Definitions (Continued)
††
Hold after WR# High
Definition