Intel 8XC196K Series User Manual page 166

During a reception, the RI flag in SP_STATUS is set after the stop bit is sampled. The RI pending
bit in the interrupt pending register is set immediately before the RI flag is set. During a transmis-
sion, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted. TheTI
pending bit in the interrupt pending register is generated when the TI flag in SP_STATUS is set.
Clock Inhibit
Serial In
V
CC
Serial
In B
Clear
Figure 7-2. Typical Shift Register Circuit for Mode 0
TXD
RXD (OUT)
RXD (IN)
Expanded:
XTAL1
TXD
RXD (OUT)
RXD (IN)
Q#
Shift Register
74HC165
Inputs
Outputs
Shift Register
74HC164
D0 D1 D2
D0 D1 D2
D0
D0
Figure 7-3. Mode 0 Timing
Shift / LOAD#
V
CC
74HC05
15KΩ
Serial In A
Clock
D3 D4 D5
D3 D4 D5
D1
D1
SERIAL I/O (SIO) PORT
P x . x
Data
RXD
Clock
TXD
8XC196
Device
Enable#
P x . x
A0264-02
D6 D7
D6 D7
D2
A0109-02
7-5