Intel 8XC196K Series User Manual page 487

Table of Contents

8XC196K x , J x , CA USER'S MANUAL

Table A-8. Instruction Lengths and Hexadecimal Opcodes

ADDB (2 ops)

ADDB (3 ops)

SUBB (2 ops)

SUBB (3 ops)

Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed

modes. Because word registers always have even addresses, the address can be expressed in the

upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-

indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and

long-indexed modes make the second byte odd (LSB = 1).

For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed

instruction length and L is the long-indexed instruction length.

For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated

with the eight bits to form an 11-bit, 2's complement offset.

Arithmetic (Group I)

(Notes 1, 2)