Intel 8XC196K Series User Manual page 115

Table of Contents

8XC196K x , J x , CA USER'S MANUAL

The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt

has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre-

sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the

end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set

manually to re-enable the PTS channel.

This bit is set by hardware to request an end-of-PTS interrupt for the corresponding

interrupt through its standard interrupt vector.

The standard interrupt vector locations are as follows.

Bit Mnemonic Interrupt

This bit is cleared when all EPA interrupt pending bits (EPA_PEND and EPA_PEND1)

are cleared.

Bit 13 is reserved on the 8XC196J x , K x devices and bits 6–8 are reserved on the 87C196CA,

8XC196J x devices. For compatibility with future devices, write zeros to these bits.

CAN Peripheral

SIO Transmit

SSIO1 Transfer

SSIO0 Transfer

Slave Port Command Buffer Full

Slave Port Input Buffer Full

Slave Port Output Buffer Empty

A/D Conversion Complete

EPA Capture/Compare Channel 0

EPA Capture/Compare Channel 1

EPA Capture/Compare Channel 2

EPA Capture/Compare Channel 3

Multiplexed EPA

Figure 5-10. PTS Service (PTSSRV) Register

Reset State:

Standard Vector