Intel 8XC196K Series User Manual page 512

Name Type
CPVER O
EA# I
EPA9:0 (K x ) I/O
EPA9:8,
EPA3:0
(J x , CA)
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
Table B-6. Signal Descriptions (Continued)
Cumulative Program Verification
During slave programming, a high signal indicates that all locations
programmed correctly, while a low signal indicates that an error occurred during
one of the programming operations.
On the 8XC196K x , CPVER is multiplexed with P2.6 and HLDA#.
On the 8XC196J x and 87C196CA, CPVER is multiplexed with P2.6 and
ONCE#.
External Access
EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect. Accesses to special-purpose and program
memory partitions are directed to internal memory if EA# is held high and to
external memory if EA# is held low. (See Table 4-1 on page 4-2 for address
ranges of special-purpose and program memory partitions.)
EA# also controls program mode entry. If EA# is at V
+12.5 V) on the rising edge of RESET#, the device enters programming mode.
NOTE: When EA# is active, ports 3 and 4 will function only as the
address/data bus. They cannot be used for standard I/O.
On devices with no internal nonvolatile memory, always connect EA# to V
Event Processor Array (EPA) Input/Output pins
These are the high-speed input/output pins for the EPA capture/compare
channels. For high-speed PWM applications, the outputs of two EPA channels
(either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a
PWM waveform on a shared output pin (see "Generating a High-speed PWM
Output" on page 10-16).
EPA9:0 are multiplexed as follows: EPA0/P1.0/T2CLK, EPA1/P1.1,
EPA2/P1.2/T2DIR, EPA3/P1.3, EPA4/P1.4, EPA5/P1.5, EPA6/P1.6, EPA7/P1.7,
EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1.
EPA7:4 are not implemented on the 8XC196J x or 87C196CA.
SIGNAL DESCRIPTIONS
Description
voltage (typically
PP
.
SS
B-11