Intel 8XC196K Series User Manual page 517

8XC196K x , J x , CA USER'S MANUAL
Name Type
O
PVER
RD# O
READY I
RESET# I/O
RXCAN I
(CA only)
RXD I/O
SC1:0 I/O
SD1:0 I/O
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B-16
Table B-6. Signal Descriptions (Continued)
Program Verification
During slave or auto programming, PVER is updated after each programming
pulse. A high output signal indicates successful programming of a location,
while a low signal indicates a detected error.
PVER is multiplexed with P2.0 and TXD.
Read
Read-signal output to external memory. RD# is asserted only during external
memory reads.
RD# is multiplexed with P5.3 and SLPRD#.
Ready Input
This active-high input signal is used to lengthen external memory cycles for
slow memory by generating wait states in addition to the wait states that are
generated internally.
When READY is high, CPU operation continues in a normal manner with wait
states inserted as programmed in the chip configuration registers. READY is
ignored for all internal memory accesses.
READY is multiplexed with P5.6.
Reset
A level-sensitive reset input to and open-drain system reset output from the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times. In the
powerdown and idle modes, asserting RESET# causes the chip to reset and
return to normal operating mode. The microcontroller resets to 2080H.
Receive
This signal carries messages from other nodes on the CAN bus to the
integrated CAN controller.
Receive Serial Data
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it
functions as either an input or an open-drain output for data.
RXD is multiplexed with P2.1 and PALE#.
Clock Pins for SSIO0 and 1
For handshaking mode, configure SC1:0 as open-drain outputs.
This pin carries a signal only during receptions and transmissions. When the
SSIO port is idle, the pin remains either high (with handshaking) or low (without
handshaking).
SC0 is multiplexed with P6.4. SC1 is multiplexed with P6.6.
Data Pins for SSIO0 and 1
SD0 is multiplexed with P6.5. SD1 is multiplexed with P6.7.
Description