Intel 8XC196K Series User Manual page 546

Table of Contents

CAN_MSG x CON0 (Continued)

x = 1–15 (87C196CA)

Program the CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the

message object is ready to transmit and to control whether a successful transmission or reception

generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending.

This register consists of four bit-pairs — the most-significant bit of each pair is in true form and the

least-significant bit is in complement form. This format allows software to set or clear any bit with a

single write operation, without affecting the remaining bits.

Table C-5. CAN_MSG x CON0 Addresses and Reset Values

CAN_MSG1CON0

CAN_MSG2CON0

CAN_MSG3CON0

CAN_MSG4CON0

CAN_MSG5CON0

CAN_MSG6CON0

CAN_MSG7CON0

CAN_MSG8CON0

After reset, this register contains the value that was written to it before reset.

Receive Interrupt Enable

Transmit message objects do not use this bit-pair.

For a receive message object, set this bit-pair to enable this message

object to initiate a receive (RX) interrupt after a successful reception. You

must also set the interrupt enable bit (CAN_CON.1) to enable the interrupt.

no interrupt

generate an interrupt

Interrupt Pending

This bit-pair indicates that this message object has initiated a transmit (TX)

or receive (RX) interrupt. Software must clear this bit when it services the

no interrupt

an interrupt was generated

Reset State:

CAN_MSG9CON0

CAN_MSG10CON0

CAN_MSG11CON0

CAN_MSG12CON0

CAN_MSG13CON0

CAN_MSG14CON0

CAN_MSG15CON0

CAN_MSGxCON0