Enabling The Epa Interrupts - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
COMP x _CON
(Continued)
x = 0–1
The EPA compare control (COMP x _CON) registers determine the function of the EPA compare
channels.
7
TB CE
Bit Bit
Number Mnemonic
2 AD
1 ROT
0 RT
Figure 10-11. EPA Compare Control (COMP x _CON) Registers (Continued)

10.6 ENABLING THE EPA INTERRUPTS

The EPA generates four individual event interrupts, EPA0–EPA3, and the multiplexed event in-
terrupt, EPAx. To enable the interrupts, set the corresponding bits in the INT_MASK register
(Figure 5-5 on page 5-13). To enable the individual sources of the multiplexed EPAx interrupt,
set the corresponding bits in the EPA_MASK (Figure 10-12) and EPA_MASK1(Figure 10-13)
registers. (Chapter 5, "Standard and PTS Interrupts," discusses the interrupts in greater detail.)
10-26
M1 M0
A/D Conversion
Allows the EPA to start an A/D conversion that has been previously set
up in the A/D control registers. To use this feature, you must select the
EPA as the conversion source in the AD_CONTROL register.
1 = EPA compare event triggers an A/D conversion
0 = causes no A/D action
Reset Opposite Timer and Reset Timer
These bits control whether an EPA compare event resets the reference
timer or the opposite timer.
ROT RT
X 0 reset function disabled
0 1 resets reference timer
1 1 resets opposite timer
The state of the TB bit (COMP x _CON.7) determines which timer is the
reference timer and which timer is the opposite timer.
Reset Timer
This bit controls whether the timer selected by the ROT bit will be reset
1 = resets the timer selected by the ROT bit
0 = disables the reset function
Address:
Reset State:
RE AD ROT
Function
x = 0, 1F88H
x = 1, 1F8CH
00H
0
RT