Pts Interrupt Latency - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
5.4.2.2

PTS Interrupt Latency

The maximum delay for a PTS interrupt is 43 state times (4 + 39). This delay time does not in-
clude the added delay if a protected instruction is being executed or if a PTS request is already in
progress. See Table 5-4 for execution times for PTS routines.
Execution
EXTINT
Pending
Interrupt
Response Time
PTS Mode
Single transfer mode
register/register
memory/register
memory/memory
Block transfer mode
register/register
memory/register
memory/memory
A/D scan mode
register/register
register/memory
PWM remap mode
PWM toggle mode
†
Register indicates an access to the register file or peripheral SFR. Memory indicates
an access to a memory-mapped register, I/O, or memory. See Table 4-1 on page 4-2 for
address information.
5-10
39
4 3 2 1
Ending
"NORML"
Instruction
Set
Latency Time
43 State Times
Figure 5-3. PTS Interrupt Response Time
Table 5-4. Execution Times for PTS Cycles
†
18 per byte or word transfer + 1
†
21 per byte or word transfer + 1
†
24 per byte or word transfer + 1
†
13 + 7 per byte or word transfer (1 minimum)
†
16 + 7 per byte or word transfer (1 minimum)
†
19 + 7 per byte or word transfer (1 minimum)
†
21
†
25
15
15
End Vector to PTS
"NORML" Control Block
PTS Interrupt Routine
Cleared
Execution Time (in State Times)
PTS
PTS
A0142-01