Intel 8XC196K Series User Manual page 596

Table of Contents

The serial port control (SP_CON) register selects the communications mode and enables or disables

the receiver, parity checking, and nine-bit data transmission.

CA, J x , KQ, KR

This bit is reserved on the 87C196CA, 8XC196J x , KQ, KR devices. For compatibility with future

devices, write zero to this bit.

Reserved; always write as zeros.

Parity Selection Bit

Selects even or odd parity.

1 = odd parity

0 = even parity

Transmit Ninth Data Bit

This is the ninth data bit that will be transmitted in mode 2 or 3. This bit

is cleared after each transmission, so it must be set before SBUF_TX is

written. When SP_CON.2 is set, this bit takes on the even parity value.

Receive Enable

Setting this bit enables the receiver function of the RXD pin. When this

bit is set, a high-to-low transition on the pin starts a reception in mode 1,

2, or 3. In mode 0, this bit must be clear for transmission to begin and

must be set for reception to begin. Clearing this bit stops a reception in

progress and inhibits further receptions.

Parity Enable

In modes 1 and 3, setting this bit enables the parity function. This bit

must be cleared if mode 2 is used. When this bit is set, TB8 takes the

parity value on transmissions. With parity enabled, SP_STATUS.7

becomes the receive parity error bit.

Mode Selection

These bits select the communications mode.

Reset State: