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Page 1 8XC196NT Microcontroller User’s Manual...
Page 2 8XC196NT Microcontroller User’s Manual June 1995 Order Number 272317-003...
Page 3 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Page 4: Table Of Contents
CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL MANUAL CONTENTS ....................1-1 NOTATIONAL CONVENTIONS AND TERMINOLOGY ..........1-3 RELATED DOCUMENTS ....................1-5 ELECTRONIC SUPPORT SYSTEMS ................1-8 1.4.1 FaxBack Service .......................1-8 1.4.2 Bulletin Board System (BBS) ..................1-9 ® 1.4.2.1 How to Find MCS 96 Microcontroller Files on the BBS ........1-9 1.4.2.2 How to Find Ap BUILDER Software and Hypertext Documents on the BBS ..1-10...
Page 5 8XC196NT USER’S MANUAL 2.6.3 Programming the Nonvolatile Memory ..............2-11 CHAPTER 3 PROGRAMMING CONSIDERATIONS OVERVIEW OF THE INSTRUCTION SET..............3-1 3.1.1 BIT Operands ......................3-2 3.1.2 BYTE Operands ......................3-2 3.1.3 SHORT-INTEGER Operands ..................3-2 3.1.4 WORD Operands ......................3-3 3.1.5 INTEGER Operands ....................3-3 3.1.6 DOUBLE-WORD Operands ..................3-3...
Page 6 Example 1: A 64-Kbyte Mode 87C196NT System ..........4-28 4.6.2 Example 2: A 64-Kbyte 87C196NT System with Additional Data Storage ....4-30 4.6.3 Example 3: A 1-Mbyte 87C196NT System with a 16-bit Bus ........4-32 4.6.4 Example 4: A 1-Mbyte 8XC196NT System with an 8-bit Bus .........4-34...
Page 7 8XC196NT USER’S MANUAL CHAPTER 5 STANDARD AND PTS INTERRUPTS OVERVIEW OF INTERRUPTS..................5-1 INTERRUPT SIGNALS AND REGISTERS ..............5-3 INTERRUPT SOURCES AND PRIORITIES..............5-4 5.3.1 Special Interrupts ......................5-6 5.3.1.1 Unimplemented Opcode ..................5-6 5.3.1.2 Software Trap .......................5-6 5.3.1.3 NMI ........................5-6 5.3.2 External Interrupt Pins ....................5-6...
Page 8 CONTENTS 6.3.3 Bidirectional Port Pin Configuration Example ............6-10 6.3.4 Bidirectional Port Considerations ................6-11 6.3.5 Design Considerations for External Interrupt Inputs ..........6-14 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)........6-14 6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation ........6-15 6.4.2 Using Ports 3 and 4 as I/O ..................6-17 6.4.3 Design Considerations for Ports 3 and 4 ..............6-18...
Page 9 8XC196NT USER’S MANUAL CHAPTER 8 SYNCHRONOUS SERIAL I/O (SSIO) PORT SYNCHRONOUS SERIAL I/O (SSIO) PORT FUNCTIONAL OVERVIEW....8-1 SSIO PORT SIGNALS AND REGISTERS ..............8-2 SSIO OPERATION ......................8-3 SSIO HANDSHAKING ....................8-6 8.4.1 SSIO Handshaking Configuration ................8-6 8.4.2 SSIO Handshaking Operation ...................8-7 PROGRAMMING THE SSIO PORT ................
Page 10 CONTENTS 10.3.2 Quadrature Clocking Mode ..................10-7 10.4 EPA CHANNEL FUNCTIONAL OVERVIEW ............... 10-9 10.4.1 Operating in Capture Mode ...................10-11 10.4.1.1 Handling EPA Overruns ...................10-12 10.4.2 Operating in Compare Mode .................10-13 10.4.2.1 Generating a Low-speed PWM Output ............10-14 10.4.2.2 Generating a Medium-speed PWM Output ............10-15 10.4.2.3 Generating a High-speed PWM Output ............10-16 10.4.2.4...
Page 11 8XC196NT USER’S MANUAL CHAPTER 12 MINIMUM HARDWARE CONSIDERATIONS 12.1 MINIMUM CONNECTIONS ..................12-1 12.1.1 Unused Inputs ......................12-2 12.1.2 I/O Port Pin Connections ..................12-2 12.2 APPLYING AND REMOVING POWER ............... 12-4 12.3 NOISE PROTECTION TIPS ..................12-4 12.4 PROVIDING THE CLOCK ................... 12-5 12.4.1...
Page 12 CONTENTS 14.4.3 8-bit Bus Timings ....................14-15 14.5 WAIT STATES (READY CONTROL)................. 14-17 14.6 BUS-HOLD PROTOCOL ................... 14-19 14.6.1 Enabling the Bus-hold Protocol ................14-21 14.6.2 Disabling the Bus-hold Protocol ................14-22 14.6.3 Hold Latency ......................14-22 14.6.4 Regaining Bus Control ..................14-22 14.7 BUS-CONTROL MODES................... 14-23 14.7.1 Standard Bus-control Mode ..................14-23 14.7.2...
Page 13 8XC196NT USER’S MANUAL 15.8.5 Timing Mnemonics ....................15-24 15.9 AUTO PROGRAMMING MODE ................15-25 15.9.1 Auto Programming Circuit and Memory Map ............15-25 15.9.2 Operating Environment ..................15-27 15.9.3 Auto Programming Routine ...................15-27 15.9.4 Auto Programming Procedure ................15-29 15.9.5 ROM-dump Mode ....................15-30 15.10 SERIAL PORT PROGRAMMING MODE ..............15-31 15.10.1 Serial Port Programming Circuit and Memory Map ..........15-31...
Page 14 CONTENTS FIGURES Figure Page 8XC196NT Block Diagram ...................2-2 Block Diagram of the Core ...................2-2 Clock Circuitry ......................2-6 Internal Clock Phases ....................2-7 16-Mbyte Address Space .....................4-2 Pages FFH and 00H.....................4-3 Internal RAM Control (IRAM_CON) Register .............4-11 Register File Memory Map ..................4-12 Windowing ........................4-15...
Page 15 8XC196NT USER’S MANUAL FIGURES Figure Page Serial Port Frames in Mode 2 and 3................7-7 Serial Port Control (SP_CON) Register................7-9 Serial Port Baud Rate (SP_BAUD) Register ..............7-10 Serial Port Status (SP_STATUS) Register..............7-12 SSIO Block Diagram ....................8-1 SSIO Operating Modes ....................8-4 SSIO Transmit/Receive Timings ..................8-6 SSIO Handshaking Flow Diagram................8-7...
Page 16 CONTENTS FIGURES Figure Page 11-11 Terminal-based A/D Conversion Characteristic ............11-19 12-1 Minimum Hardware Connections ................12-3 12-2 Power and Return Connections .................12-4 12-3 On-chip Oscillator Circuit....................12-6 12-4 External Crystal Connections ..................12-7 12-5 External Clock Connections ..................12-8 12-6 External Clock Drive Waveforms................12-8 12-7 Reset Timing Sequence .....................12-9 12-8...
Page 17 Program Word Waveform..................15-22 15-10 Dump Word Routine ....................15-23 15-11 Dump Word Waveform .....................15-24 15-12 Auto Programming Circuit ..................15-26 15-13 Auto Programming Routine ..................15-28 15-14 Serial Port Programming Mode Circuit ..............15-32 15-15 Run-time Programming Code Example..............15-44 8XC196NT 68-lead PLCC Package ................B-3...
Page 18 8XC196NT Special-purpose Memory Addresses............4-7 8XC196NT Memory-mapped SFRs................4-9 8XC196NT Peripheral SFRs ..................4-10 Register File Memory Addresses ................4-13 8XC196NT CPU SFRs ....................4-14 Selecting a Window of 8XC196NT Peripheral SFRs..........4-16 4-10 Selecting a Window of the Upper Register File ............4-17 4-11 Windows ........................4-18 4-12 Windowed Base Addresses ..................4-19...
Page 19 8XC196NT USER’S MANUAL TABLES Table Page Bidirectional Port Pins ....................6-4 Bidirectional Port Control and Status Registers ............6-5 Logic Table for Bidirectional Ports in I/O Mode ............6-8 Logic Table for Bidirectional Ports in Special-function Mode ........6-8 Control Register Values for Each Configuration............6-10 Port Configuration Example ..................6-10...
Page 20 Instruction Lengths and Hexadecimal Opcodes ............A-52 Instruction Execution Times (in State Times) ............A-59 Signal Name Changes ....................B-1 8XC196NT Signals Arranged by Functional Categories ..........B-2 Description of Columns of Table B-4................B-4 Signal Descriptions...................... B-4 Definition of Status Symbols ..................B-14 8XC196NT Pin Status ....................
Page 21 8XC196NT USER’S MANUAL TABLES Table Page C-13 Common SSIO_BAUD Values When Using XTAL1 at 20 MHz ........ C-57 SSIO x _BUF Addresses and Reset Values..............C-58 C-14 C-15 SSIO x _CON Addresses and Reset Values............... C-60 C-16 TIMER x Addresses and Reset Values ..............C-63 C-17 WSR Settings and Direct Addresses for Windowable SFRs ........
Page 22: Guide To This Manual
Guide to This Manual...
Page 24: Manual Contents
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196NT embedded microcontroller. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you complete your design.
Page 25 8XC196NT USER’S MANUAL Chapter 8 — Synchronous Serial I/O (SSIO) Port — describes the synchronous serial I/O (SSIO) port and explains how to program it. Chapter 9 — Slave Port — describes the slave port and explains how to program it. Chapter 6, “I/O Ports,”...
Page 26: Notational Conventions And Terminology
GUIDE TO THIS MANUAL Appendix C — Registers — provides a compilation of all device registers arranged alphabeti- cally by register mnemonic. It also includes tables that list the windowed direct addresses for all SFRs in each possible window. Glossary — defines terms with special meaning used throughout this manual. Index —...
Page 27 8XC196NT USER’S MANUAL italics Italics identify variables and introduce new terminology. The context in which italics are used distinguishes between the two possible meanings. Variables in registers and signal names are commonly represented by x and y, where x represents the first variable and y represents the second variable.
Page 28: Related Documents
For a complete list of available printed documents, please or- der the literature catalog (order number 210621). To order documents, please call the Intel literature center for your area (telephone numbers are listed on page 1-11).
Page 29 Complete set of Intel handbooks on CD-ROM. Handbook Set — handbooks and product overview 231003 Complete set of Intel’s product line handbooks. Contains datasheets, application notes, article reprints and other design information on microprocessors, periph- erals, embedded controllers, memory components, single-board computers, microcommunications, software development tools, and operating systems.
Page 30 272323 † 87C196MD Industrial Motor Control CHMOS Microcontroller 270946 † 8XC196NP Commercial CHMOS 16-Bit Microcontroller 272459 8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space † 272267 † Included in Embedded Microcontrollers handbook (order number 270646) ® Table 1-4. MCS 96 Microcontroller Datasheets (Automotive)
Page 31: Electronic Support Systems
8XC196NT USER’S MANUAL ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information. We also maintain several forums on CompuServe and offer a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical information whenever you need it.
Page 32: Bulletin Board System (Bbs)
Application notes, utilities, and product literature are available from the BBS. To access the files, complete these steps: Enter F from the BBS Main menu. The BBS displays the Intel Apps Files menu. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area number.
Page 33: How To Find Ap Builder Software And Hypertext Documents On The Bbs
BBS. To access the files, complete these steps: Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area number.
Page 34: Technical Support
Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only) TRAINING CLASSES In the U.S. and Canada, you can register for training classes through the Intel customer training center. Classes are held in the U.S. 1-800-234-8806 U.S. and Canada 1-11...
Page 36: Architectural Overview
Architectural Overview...
Page 38: Typical Applications
CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196NT CHMOS microcontroller is designed to handle high-speed calculations and fast input/output (I/O) operations. It shares a common architecture and instruction set with ® other members of the MCS 96 microcontroller family. This device extends the addressability of the MCS 96 family to 1 Mbyte.
Page 39 Partitions,” and Chapter 6, “I/O Ports,” for additional information.) Optional Interrupt Core Controller Clock and Code/Data Power Mgmt. Slave SSIO Port A2800-01 Figure 2-1. 8XC196NT Block Diagram Memory Controller Register File RALU Prefetch Queue Microcode Engine Slave PC Register Address Register Data Register Master PC...
Page 40: Cpu Control
ARCHITECTURAL OVERVIEW 2.3.1 CPU Control The CPU is controlled by the microcode engine, which instructs the RALU to perform operations using bytes, words, or double words from either the 256-byte lower register file or through a win- dow that directly accesses the upper register file. (See Chapter 4, “Memory Partitions,” for more information about the register file and windowing.) CPU instructions move from the 4-byte queue in the memory controller into the RALU’s instruction register.
Page 41: Code Execution
8XC196NT USER’S MANUAL All registers, except the 3-bit bit-select register and the 6-bit loop counter, are either 16 or 17 bits (16 bits plus a sign extension). Some of these registers can reduce the ALU’s workload by per- forming simple operations.
Page 42: Memory Controller
ARCHITECTURAL OVERVIEW 2.3.4 Memory Controller The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory control- ler except when windowing is used; see Chapter 4, “Memory Partitions,”) The memory controller contains the prefetch queue, the slave program counter (slave PC), address and data registers, and the bus controller.
Page 43: Internal Timing
8XC196NT USER’S MANUAL The PTS can transfer bytes or words, either individually or in blocks, between any memory loca- tions, manage multiple analog-to-digital (A/D) conversions, and generate pulse-width modulated (PWM) signals. PTS interrupts have a higher priority than standard interrupts and may temporari- ly suspend interrupt service routines.
Page 44: Internal Peripherals
ARCHITECTURAL OVERVIEW XTAL1 1 State Time 1 State Time CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0114-02 Figure 2-4. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state.
Page 45: I/O Ports
2.5.1 I/O Ports The 8XC196NT has eight I/O ports, ports 0–6 and the EPORT. Individual port pins are multi- plexed to serve as standard I/O or to carry special-function signals associated with an on-chip pe- ripheral or an off-chip component. If a particular special-function signal is not used in an application, the associated pin can be individually configured to serve as a standard I/O pin.
Page 46: Slave Port
ARCHITECTURAL OVERVIEW 2.5.4 Slave Port The slave port offers an alternative for communication between two CPU devices. Traditionally, system designers have had three alternatives for achieving this communication — a serial link, a parallel bus without a dual-port RAM (DPRAM), or a parallel bus with a DPRAM to hold shared data.
Page 47: Analog-To-Digital Converter
8XC196NT USER’S MANUAL 2.5.6 Analog-to-digital Converter The analog-to-digital (A/D) converter converts an analog input voltage to a digital equivalent. Resolution is either 8 or 10 bits; sample and convert times are programmable. Conversions can be performed on the analog ground and reference voltage, and the results can be used to calculate gain and zero-offset errors.
Page 48: Testing The Printed Circuit Board
• Slave programming allows a master EPROM programmer to program and verify one or more slave MCS 96 microcontrollers. Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer’s code and data.
Page 50: Programming Considerations
Programming Considerations...
Page 52: Overview Of The Instruction Set
CHAPTER 3 PROGRAMMING CONSIDERATIONS ® This section provides an overview of the instruction set of the MCS 96 microcontrollers and of- fers guidelines for program development. For detailed information about specific instructions, see Appendix A. INSTRUCTION SET OVERVIEW OF THE The instruction set supports a variety of operand types likely to be useful in control applications (see Table 3-1).
Page 53: Bit Operands
8XC196NT USER’S MANUAL Table 3-2 lists the equivalent operand-type names for both C programming and assembly lan- guage. Table 3-2. Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equivalent C Programming Language Equivalent BYTE BYTE...
Page 54: Word Operands
PROGRAMMING CONSIDERATIONS 3.1.4 WORD Operands A WORD is an unsigned, 16-bit variable that can take on values from 0 through 65,535 (2 –1). Arithmetic and relational operators can be applied to WORD operands, but the result must be in- terpreted in modulo 65536 arithmetic. Logical operations on WORDs are applied bitwise. Bits within WORDs are labeled from 0 to 15;...
Page 55: Long-Integer Operands
8XC196NT USER’S MANUAL 3.1.7 LONG-INTEGER Operands A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648 (– 2 ) through +2,147,483,647 (+2 –1). The architecture directly supports LONG-INTEGER operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations.
Page 56: Floating Point Operations
PROGRAMMING CONSIDERATIONS 3.1.11 Floating Point Operations The hardware does not directly support operations on REAL (floating point) variables. Those op- erations are supported by floating point libraries from third-party tool vendors. (See the Develop- ment Tools Handbook.) The performance of these operations is significantly improved by the NORML instruction and by the sticky bit (ST) flag in the processor status word (PSW).
Page 57: Addressing Modes
8XC196NT USER’S MANUAL Extended store word. Stores the value of the source (leftmost) word operand into the destination (rightmost) operand. This instruction allows you to move data from the lower register file to anywhere in the address space. It operates in extended indirect and extended indexed modes.
Page 58: Direct Addressing
PROGRAMMING CONSIDERATIONS Table 3-3. Definition of Temporary Registers Temporary Register Description word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte word-aligned 16-bit register;...
Page 59: Extended Indirect Addressing
8XC196NT USER’S MANUAL ; AX ← MEM_WORD(BX) AX,[BX] ; AL ← BL + MEM_BYTE(CX) ADDB AL,BL,[CX] ; MEM_WORD(AX) ← MEM_WORD(SP) [AX] ; SP ← SP + 2 3.2.3.1 Extended Indirect Addressing Extended load and store instructions can use indirect addressing. The only difference is that the register containing the indirect address must be a word-aligned 24-bit register to allow access to the entire 1-Mbyte address space.
Page 60: Indirect Addressing With The Stack Pointer
PROGRAMMING CONSIDERATIONS 3.2.3.4 Indirect Addressing with the Stack Pointer You can also use indirect addressing to access the top of the stack by using the stack pointer as the WORD register in an indirect reference. The following instruction uses indirect addressing with the stack pointer: PUSH [SP] ;...
Page 61: Extended Indexed Addressing
8XC196NT USER’S MANUAL ; MEM_WORD(TABLE+BX) ← AX AX,TABLE[BX] ; AL ← BL + MEM_BYTE(LOOKUP+CX) ADDB AL,BL,LOOKUP[CX] The instruction LD AX, TABLE[BX] loads AX with the contents of the memory location that re- sides at address TABLE+BX. That is, the instruction adds the contents of BX (the offset) to the constant TABLE (the base address), then loads AX with the contents of the resulting address.
Page 62: Assembly Language Addressing Mode Selections
PROGRAMMING CONSIDERATIONS ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes. Use these features wherever possible. 3.3.1 Direct Addressing The assembly language chooses between direct and zero-indexed addressing depending on the memory location of the operand. Simply refer to the operand by its symbolic name. If the operand is in the lower register file, the assembly language chooses a direct reference.
Page 63: Using Registers
8XC196NT USER’S MANUAL 3.5.1 Using Registers The 256-byte lower register file contains the CPU special-function registers and the stack pointer. The remainder of the lower register file and all of the upper register file is available for your use. Peripheral special-function registers (SFRs) and memory-mapped SFRs reside in higher memory.
Page 64: Linking Subroutines
PROGRAMMING CONSIDERATIONS 3.5.4 Linking Subroutines Parameters are passed to subroutines via the stack. Parameters are pushed into the stack from the rightmost parameter to the left. The 8-bit parameters are pushed into the stack with the high-order byte undefined. The 32-bit parameters are pushed onto the stack as two 16-bit values; the most- significant half of the parameter is pushed into the stack first.
Page 65: Software Protection Features And Guidelines
8XC196NT USER’S MANUAL SOFTWARE PROTECTION FEATURES AND GUIDELINES The device has several features to assist in recovering from hardware and software errors. The unimplemented opcode interrupt provides protection from executing unimplemented opcodes. The hardware reset instruction (RST) can cause a reset if the program counter goes out of bounds.
Page 66: Memory Partitions
Memory Partitions...
Page 68: Memory Map Overview
CHAPTER 4 MEMORY PARTITIONS This chapter describes the organization of the address space, its major partitions, and the 1-Mbyte and 64-Kbyte operating modes. 1-Mbyte refers to the address space defined by the 20 external address lines. In 1-Mbyte mode, code can execute from almost anywhere in the 1-Mbyte space. In 64-Kbyte mode, code can execute only from the 64-Kbyte area FF0000–FFFFFFH.
Page 69 8XC196NT USER’S MANUAL Because the four MSBs of the internal address can take any values without changing the external address, these four bits effectively produce 16 copies of the 1-Mbyte address space, for a total of 16 Mbytes in 256 pages, 00H–FFH (Figure 4-1). For example, page 01H has 15 duplicates: 11H, 21H, ..., F1H.
Page 70 Upper Register File External Memory FF0100H 000100H FF00FFH 0000FFH Reserved Lower Register File FF0000H 000000H A3055-02 Figure 4-2. Pages FFH and 00H MEMORY PARTITIONS Table 4-1 is a memory map of the 8XC196NT. The remainder of this section describes the parti- tions.
Page 71 8XC196NT USER’S MANUAL Table 4-1. 8XC196NT Memory Map Description Addressing Modes Address FFFFFF External device (memory or I/O) connected to address/data bus Indirect, indexed, extended FFA000 FF9FFF Program memory (Note 1) FF2080 After a device reset, the first instruction fetch is from FF2080H Indirect, indexed, extended (or F2080H in external memory).
Page 72: External Memory
MEMORY PARTITIONS 4.2.1 External Memory Several partitions in pages 00H and FFH and all of pages 01H–0EH are assigned to external memory (see Table 4-1 on page 4-4). Data can be stored in any part of this memory. Instructions can be stored in any part of this memory in 1-Mbyte mode, but can be stored only in page FFH in 64-Kbyte mode.
Page 73: Special-Purpose Memory
8XC196NT USER’S MANUAL Table 4-2. Program Memory Access for the 87C196NT REMAP Instruction Type Memory Location Accessed (CCB2.2) extended or asserted external memory, F2080–F9FFFH nonextended extended or deasserted internal OTPROM, FF2080–FF9FFFH nonextended extended internal OTPROM, FF2080–FF9FFFH deasserted nonextended internal OTPROM, 002080–009FFFH...
Page 74: Reserved Memory Locations
MEMORY PARTITIONS Table 4-4. 8XC196NT Special-purpose Memory Addresses Address Description (Hex) FF207F Reserved (each byte must contain FFH) FF205E FF205D PTS vectors FF2040 FF203F Upper interrupt vectors FF2030 FF202F Security key FF2020 FF201F Reserved (must contain 20H for compatibility with future devices)
Page 75: Chip Configuration Bytes
4.2.3 Special-function Registers (SFRs) The 8XC196NT has both peripheral SFRs and memory-mapped SFRs. The peripheral SFRs are physically located in the on-chip peripherals. They can be addressed as bytes or as words, and they can be windowed (see “Windowing” on page 4-15). The memory-mapped SFRs must be ac- cessed using indirect or indexed addressing modes and cannot be windowed.
Page 76: Peripheral Sfrs
MEMORY PARTITIONS Table 4-5. 8XC196NT Memory-mapped SFRs Ports 3, 4, 5, Slave Port, UPROM SFRs EPORT and Internal RAM SFRs High (Odd) Byte Low (Even) Byte High (Odd) Byte Low (Even) Byte Address Address 1FFE P4_PIN P3_PIN 1FEE Reserved Reserved...
Page 77 8XC196NT USER’S MANUAL Table 4-6. 8XC196NT Peripheral SFRs Ports 0, 1, 2, and 6 SFRs Timer 1, Timer 2, and EPA SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte † 1FDEH Reserved Reserved...
Page 78: Internal Ram (Code Ram)
4.2.4 Internal RAM (Code RAM) The 8XC196NT has 512 bytes of internal code RAM in locations 0400–05FFH. This memory can be accessed from either page 00H or page FFH. Although it is called code RAM to distinguish it from register RAM, this internal RAM can store either code or data. The code RAM is accessed through the memory controller, so code executes as it would from external memory with zero wait states.
Page 79: Register File
8XC196NT USER’S MANUAL 4.2.5 Register File The register file is divided into an upper register file and a lower register file (Figure 4-4). The upper register file consists of general-purpose register RAM. The lower register file contains ad- ditional general-purpose register RAM along with the stack pointer (SP) and the CPU special- function registers (SFRs).
Page 80 MEMORY PARTITIONS Table 4-7. Register File Memory Addresses Address Description Addressing Modes Range 03FFH General-purpose register RAM Indirect or indexed addressing; direct addressing if windowed 0100H (upper register file) 00FFH General-purpose register RAM Direct, indirect, or indexed addressing 001AH (lower register file) 0019H Stack pointer (SP) Direct,indirect, or indexed addressing...
Page 81: Cpu Special-Function Registers (Sfrs)
;Load stack pointer 4.2.5.3 CPU Special-function Registers (SFRs) Locations 0000–0017H in the lower register file are the CPU SFRs (see Table 4-8). Appendix C describes the CPU SFRs. Table 4-8. 8XC196NT CPU SFRs Address High (Odd) Byte Low (Even) Byte 0016H...
Page 82: Windowing
MEMORY PARTITIONS NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results. External events can change the contents of SFRs, and some SFRs are cleared when read. For this reason, consider the implications of using an SFR as an operand in a read-modify-write instruction (e.g., XORB).
Page 83: Selecting A Window
0 1 x x x x x 64-byte window; W4:0 = window number 0 0 1 x x x x 128-byte window; W3:0 = window number Figure 4-6. Window Selection Register (WSR) Table 4-9. Selecting a Window of 8XC196NT Peripheral SFRs WSR Value WSR Value...
Page 84: Addressing A Location Through A Window
MEMORY PARTITIONS Table 4-10. Selecting a Window of the Upper Register File Register RAM WSR Value WSR Value WSR Value Locations for 32-byte Window for 64-byte Window for 128-byte Window (Hex) (00E0–00FFH) (00C0–00FFH) (0080–00FFH) 03E0–03FF 03C0–03DF 03A0–03BF 0380–039F 0360–037F 0340–035F 0320–033F 0300–031F 02E0–02FF...
Page 85 8XC196NT USER’S MANUAL Table 4-11. Windows WSR Value for Base WSR Value WSR Value 128-byte Address for 32-byte Window for 64-byte Window Window (Hex) (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Peripheral SFRs † † 1FE0 † 1FC0 1FA0 † 1F80 1F60 1F40 1F20...
Page 86: 32-Byte Windowing Example
MEMORY PARTITIONS Table 4-12. Windowed Base Addresses WSR Windowed Base Address Window Size (Base Address in Lower Register File) 32-byte 00E0H 64-byte 00C0H 128-byte 0080H Appendix C includes a table of the windowable SFRs with the window selection register values and direct addresses for each window size.
Page 87: Unsupported Locations Windowing Example
8XC196NT USER’S MANUAL 4.3.2.4 Unsupported Locations Windowing Example Assume that you wish to access location 1FE7H (the EP_PIN register, a memory-mapped SFR) with direct addressing through a 128-byte window. This location is in the range of addresses (1FE0–1FFFH) that cannot be windowed. Although you could set up the window by writing 1FH to the WSR, reading this location through the window would return FFH (all ones) and writing to it would not change the contents.
Page 88 MEMORY PARTITIONS public function2 extrn ?WSR 14h:byte 18h:word oseg var1: var2: var3: cseg function2: push ;Prolog code for wsr wsr, #?WSR ;Prolog code for wsr add var1, var2, var3 wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ****************************** The following is an example of a linker invocation to link and locate the modules and to deter- mine the proper windowing.
Page 89: Windowing And Addressing Modes
8XC196NT USER’S MANUAL This listing shows the disassembled code: 2080H ;C814 | PUSH 2082H ;B14814 | LDB WSR,#48H 2085H ;44E4E2E0 | ADD E0H,E2H,E4H 2089H ;B21814 | LDB WSR,[SP] 208CH ;65020018 | ADD SP,#02H 2090H | RET 2091H ;C814 | PUSH 2093H ;B14814...
Page 90: Remapping Internal Otprom (87C196Nt Only)
MEMORY PARTITIONS REMAPPING INTERNAL OTPROM (87C196NT ONLY) The 87C196NT’s 32 Kbytes of OTPROM are located in FF2000–FF9FFFH. By using the REMAP bit (CCB2.2) and the EA# input, you can also access these locations in internal memory page 00H or in external memory page 0FH (Table 4-13). The REMAP bit is loaded from the CCB and the value of EA# is latched upon leaving reset;...
Page 91: Fetching Code And Data In The 1-Mbyte And 64-Kbyte Modes
8XC196NT USER’S MANUAL FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES This section describes how the device fetches instructions and accesses data in the 1-Mbyte and 64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB2.1) selects the 1-Mbyte or 64-Kbyte mode.
Page 92: Using Extended Instructions
MEMORY PARTITIONS From EP_REG 16-bit Data Address Register Nonextended Address 16 15 From CPU 16-bit Data Address Register Extended Address 16 15 A2514-01 Figure 4-8. Formation of Extended and Nonextended Addresses 4.5.2.1 Using Extended Instructions The code example below illustrates the use of extended instructions to access data in page 01H. EP_REG EQU 1FE5H RSEG AT 1CH...
Page 93: Code Fetches In The 1-Mbyte Mode
8XC196NT USER’S MANUAL 4.5.3 Code Fetches in the 1-Mbyte Mode Clearing the MODE64 bit (CCB2.1) selects the 1-Mbyte mode. In this mode, code can execute from any page in the 1-Mbyte address space. An extended jump, branch, or call instruction across pages changes the EPC value to the destination page.
Page 94: Data Fetches In The 1-Mbyte And 64-Kbyte Modes
MEMORY PARTITIONS Instruction fetches from FF2000–FF9FFFH are controlled by the EA# input: • If EA# is low, code executes from external memory (page 0FH). • If EA# is high, code executes from internal OTPROM (page FFH). 4.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes Data fetches are the same in the 1-Mbyte and 64-Kbyte modes.
Page 95: Memory Configuration Examples
8XC196NT USER’S MANUAL Data accesses to 002000–009FFFH depend on the REMAP bit and the EA# input: • If remapping is disabled (CCB2.2 = 0), accesses are external. • If remapping is enabled (CCB2.2 = 1), accesses depend on EA#: — If EA# is low, accesses are external (REMAP is ignored).
Page 96 MEMORY PARTITIONS Page 00H EPORT.0 32K × 8 RAM (near data) 00600–01EFFH, 0A000–0FFFFH AD15:8 A14:8 A7:0 87C196NT D7:0 Page 00H 000000–0005FFH, 001F00–009FFFH Page FFH FF0400–FF05FFH, FF2000–FF9FFFH A15:8 AD7:0 A7:0 Page 01H BUSWIDTH 74LS373 A7:0 64K × 8 RAM (far data) 10000–1FFFFH D7:0 A3058-02...
Page 97: Example 2: A 64-Kbyte 87C196Nt System With Additional Data Storage
8XC196NT USER’S MANUAL Table 4-14. Memory Map for the System in Figure 4-9 Address Description FFFFFF Unimplemented FFA000 FF9FFF Internal OTPROM (code and far constants) FF2000 FF1FFF Unimplemented FF0600 FF05FF Internal code and data RAM (mapped from page 00H) FF0400...
Page 98 MEMORY PARTITIONS The top 64K×8 RAM stores near data at addresses 00600–01EFFH and 02000–0FFFFH. The bot- tom 64K×8 RAM stores far data at addresses 10000–1FFFFH. The bus-timing mode must be ei- ther mode 0 or mode 3 because only one address latch is used. (See “Bus Timing Modes” on page 14-34.) Table 4-14 lists the memory addresses for this example.
Page 99: Example 3: A 1-Mbyte 87C196Nt System With A 16-Bit Bus
8XC196NT USER’S MANUAL Table 4-15. Memory Map for the System in Figure 4-10 Address Description FFFFFF Unimplemented FFA000 FF9FFF Internal OTPROM (code and far constants) FF2000 FF1FFF Unimplemented FF0600 FF05FF Internal code and data RAM (mapped from page 00H) FF0400...
Page 100 MEMORY PARTITIONS The 32K×16 RAM stores far data at addresses 10000–1FFFFH; code could also execute from this RAM. The 64K×16 flash memory stores code and additional far data at addresses 20000– 3FFFFH. Because addresses 20000–3FFFFH reside in a single memory component, only one EPORT line (EPORT.1, which provides address line A17) is necessary.
Page 101: Example 4: A 1-Mbyte 8Xc196Nt System With An 8-Bit Bus
000000 4.6.4 Example 4: A 1-Mbyte 8XC196NT System with an 8-bit Bus Figure 4-12 on page 4-35 illustrates a system designed to operate in 1-Mbyte mode (CCB2.1=0). Code can execute from any page in the 1-Mbyte address space. EA# is held low, so accesses to FF2000–FF9FFFH are external and the REMAP bit is ignored.
Page 102 Page 00H Chip-select Logic EPORT.1 EPORT.0 64K × 8 Flash (near data) BUSWIDTH 00600–01EFFH, 02000–0FFFFH A15:8 AD15:8 A7:0 D7:0 8XC196NT Page 00H CE1# 000000–0005FFH, 001F00–001FFFH Page 01H 64K × 8 RAM A7:0 AD7:0 (code or far data) 74LS373 10000–1FFFFH A15:8...
Page 103 8XC196NT USER’S MANUAL The 64K×8 RAM stores far data at addresses 10000–1FFFFH; code could also execute from this RAM. The top 64K×8 flash memory stores near data at addresses 00600–01EFFH and 02000– 0FFFH. The bottom 64K×8 flash memory stores code, special-purpose memory, and far data at addresses F0000–FFFFFH.
Page 104: Standard And Pts Interrupts
Standard and PTS Interrupts...
Page 106: Overview Of Interrupts
CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It discusses the three special interrupts and the five PTS modes, two of which are used with the EPA to produce pulse-width modulated (PWM) out- puts.
Page 107 8XC196NT USER’S MANUAL Interrupt Pending or PTSSRV Bit Set Pending INT_MASK. x Return = 1? Interrupts Return Enabled? Enabled PTSSEL. x Bit = 1? Priority Encoder Highest Priority Interrupt Priority Encoder Highest Priority PTS Interrupt PTSSRV. x = 1? Reset INT_PEND. x Reset PTSSRV.
Page 108: Interrupt Signals And Registers
STANDARD AND PTS INTERRUPTS Figure 5-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” repre- sents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both the INT_PEND and INT_PEND1 registers. INTERRUPT SIGNALS AND REGISTERS Table 5-1 describes the external interrupt signals and Table 5-2 describes the control and status registers for both the interrupt controller and PTS.
Page 109: Interrupt Sources And Priorities
8XC196NT USER’S MANUAL Table 5-2. Interrupt and PTS Control and Status Registers (Continued) Mnemonic Address Description EPA_PEND 1FA2H, 1FA3H EPA Interrupt Pending Registers EPA_PEND1 1FA6H The bits in these registers are set by hardware to indicate that a multiplexed EPA interrupt is pending.
Page 110 STANDARD AND PTS INTERRUPTS lects the corresponding vector location in special-purpose memory. This vector contains the start- ing (base) address of the corresponding PTS control block (PTSCB) or interrupt service routine. PTSCBs must be located on a quad-word boundary, in the internal register file. Interrupt service routines must begin execution in page FFH, but can jump anywhere after the initial vector is tak- Table 5-3.
Page 111: Special Interrupts
8XC196NT USER’S MANUAL 5.3.1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled: unimplemented opcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts) and DI (disable interrupts) instructions, and they cannot be masked. All of these interrupts are serviced by the interrupt controller;...
Page 112: Multiplexed Interrupt Sources
STANDARD AND PTS INTERRUPTS 5.3.3 Multiplexed Interrupt Sources The EPAx interrupt is generated by a group of multiplexed interrupt sources. The EPA4–9 and COMP0–1 event interrupts, the EPA0–9 overrun interrupts, and the timer 1 and timer 2 over- flow/underflow interrupts are multiplexed into EPAx. Generally, PTS interrupt service is not use- ful for multiplexed interrupts because the PTS cannot readily determine the interrupt source.
Page 113: Situations That Increase Interrupt Latency
8XC196NT USER’S MANUAL 5.4.1 Situations that Increase Interrupt Latency If an interrupt request occurs while any of the following instructions are executing, the interrupt will not be acknowledged until after the next instruction is executed: • the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions •...
Page 114: Standard Interrupt Latency
STANDARD AND PTS INTERRUPTS 5.4.2.1 Standard Interrupt Latency In 64-Kbyte mode, the worst-case delay for a standard interrupt is 56 state times (4 + 39 + 11 + 2) if the stack is in external memory. In 1-Mbyte mode, the worst-case delay increases to 61 state times (4 + 39 + 15 + 3).
Page 115: Programming The Interrupts
8XC196NT USER’S MANUAL 64-Kbyte or 1-Mbyte Mode Ending Vector to PTS "NORML" Execution Instruction "NORML" Control Block PTS Interrupt Routine Interrupt Interrupt Cleared Pending Bit Latency Time Response Time 43 State Times 64-Kbyte or 1-Mbyte Mode A0262-02 Figure 5-3. PTS Interrupt Response Time Table 5-4.
Page 116: Programming The Multiplexed Interrupts
STANDARD AND PTS INTERRUPTS To disable any interrupt, clear its mask bit. To enable an interrupt for standard interrupt service, set its mask bit and clear its PTS select bit. To enable an interrupt for PTS service, set both the mask bit and the PTS select bit.
Page 117 8XC196NT USER’S MANUAL Address: 0004H PTSSEL Reset State: 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine.
Page 118 STANDARD AND PTS INTERRUPTS Address: 0008H INT_MASK Reset State: The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the stack and POPF or POPA restores it.
Page 119: Modifying Interrupt Priorities
8XC196NT USER’S MANUAL Address: 0013H INT_MASK1 Reset State: The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
Page 120 STANDARD AND PTS INTERRUPTS SERIAL_RI_ISR: PUSHA ; Save PSW, INT_MASK, INT_MASK1, & WSR ; (this disables all interrupts) LDB INT_MASK1, #01000000B ; Enable EXTINT only ; Enable interrupt servicing ; Service the RI interrupt POPA ; Restore PSW, INT_MASK, INT_MASK1, & ;...
Page 121: Determining The Source Of An Interrupt
8XC196NT USER’S MANUAL At the end of the service routine, the POPA instruction restores the original contents of the PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these registers during the interrupt service routine are overwritten. Because interrupt calls cannot occur immediately following a POPA instruction, the last instruction (RET) will execute before another interrupt call can occur.
Page 122 STANDARD AND PTS INTERRUPTS Address: 0009H INT_PEND Reset State: When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. EPA0 EPA1 EPA2...
Page 123: Initializing The Pts Control Blocks
8XC196NT USER’S MANUAL Address: 0012H INT_PEND1 Reset State: When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
Page 124: Specifying The Pts Count
STANDARD AND PTS INTERRUPTS Single Block A/D Scan PWM Toggle PWM Remap Transfer Transfer Mode Mode Mode Unused Unused Unused PTSCONST2 (H) Unused Unused PTSBLOCK Unused PTSCONST2 (L) Unused PTSDST(H) PTSDST (H) PTSPTR2 (H) PTSCONST1 (H) PTSCONST1 (H) PTSDST (L) PTSDST (L) PTSPTR2 (L) PTSCONST1 (L)
Page 125: Selecting The Pts Mode
8XC196NT USER’S MANUAL Address: 0006H PTSSRV Reset State: 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre- sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt.
Page 126: Single Transfer Mode
STANDARD AND PTS INTERRUPTS Address: PTSPCB + 1 PTSCON The PTS control (PTSCON) register selects the PTS mode and sets up control functions for that mode. † † † † † Function Number Mnemonic M2:0 PTS Mode These bits select the PTS mode: block transfer reserved PWM toggle or remap...
Page 127 8XC196NT USER’S MANUAL PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). Unused Unused PTSDST (HI) PTS Destination Address (high byte)
Page 128 STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode single transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer † Update PTSSRC 0 = reload original PTS source address after each byte or word transfer 1 = retain current PTS source address after each byte or word...
Page 129: Block Transfer Mode
8XC196NT USER’S MANUAL Table 5-5. Single Transfer Mode PTSCB Unused Unused PTSDST (HI) = 60H PTSDST (LO) = 00H PTSSRC (HI) = 00H PTSSRC (LO) = 20H PTSCON = 85H (Mode = 100, DI & DU = 1, BW = 0) PTSCOUNT = 09H 5.6.4...
Page 130 STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). Unused PTSBLOCK PTS Block Size...
Page 131: A/D Scan Mode
8XC196NT USER’S MANUAL PTS Block Transfer Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits select the PTS mode: block transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer...
Page 132 STANDARD AND PTS INTERRUPTS PTS A/D Scan Mode Control Block In A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results. The control block contains pointers to both the AD_RESULT register (PTSPTR1) and a table of A/D conversion commands and results (PTSPTR2), a control register (PTSCON), and a A/D conversion count (PTSCOUNT).
Page 133 8XC196NT USER’S MANUAL PTS A/D Scan Mode Control Block (Continued) PTSCOUNT PTSCB + 0 Consecutive A/D Conversions Defines the number of A/D conversions that will be completed during the A/D scan routine. Each cycle consists of the PTS transferring the A/D conversion results into the command/data table, and then loading a new command into the AD_COMMAND register.
Page 134: A/D Scan Mode Cycles
STANDARD AND PTS INTERRUPTS 5.6.5.1 A/D Scan Mode Cycles Software must start the first A/D conversion. After the A/D conversion complete interrupt ini- tiates the PTS routine, the following actions occur. The PTS reads the first command (from address XXXX), stores it in a temporary location, and increments the PTSPTR1 register twice.
Page 135: A/D Scan Mode Example 2
8XC196NT USER’S MANUAL version. Step 4 updates PTSPTR1 (PTSPTR1 now points to 3004H) and step 5 decrements PTSCOUNT to 3. The next cycle begins by storing the channel 5 command in the temporary lo- cation. During the last cycle (PTSCOUNT = 1), the dummy command is loaded into the AD_COMMAND register and no conversion is performed.
Page 136: Pwm Modes
STANDARD AND PTS INTERRUPTS Table 5-11. A/D Scan Mode PTSCB (Example 2) Unused Unused PTSPTR2 (HI) = 1FH PTSPTR2 (LO) = AAH PTSPTR1 (HI) = 30H PTSPTR1 (LO) = 00H PTSCON = C3H (Mode = 110, UPDT = 0) PTSCOUNT = 0AH Software starts a conversion on channel x.
Page 137 8XC196NT USER’S MANUAL Table 5-12. Comparison of PWM Modes PWM Toggle Mode PWM Remap Mode Uses a single EPA channel. Uses two EPA channels. Reads the location specified by PTSPTR1 Reads the location specified by PTSPTR1 (usually EPA x _TIME).
Page 138: Pwm Toggle Mode Example
STANDARD AND PTS INTERRUPTS 5.6.6.1 PWM Toggle Mode Example Figure 5-16 shows the PTS control block for PWM toggle mode. To generate a PWM waveform using PWM toggle mode and EPA0, complete the following procedure. This example uses the values stored in CSTORE1 and CSTORE2 to control the frequency and duty cycle of a PWM. Disable the interrupts and the PTS.
Page 139 8XC196NT USER’S MANUAL Enable the EPA0 interrupt and select PTS service for it: — Set INT_MASK.4 — Set PTSSEL.4 Enable the interrupts and the PTS. The EI instruction enables interrupts; the EPTS instruction enables the PTS. PTS PWM Toggle Mode Control Block In PWM toggle mode, the PTS uses a single EPA channel to generate a pulse-width modulated (PWM) output signal.
Page 140 STANDARD AND PTS INTERRUPTS PTS PWM Toggle Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits specify the PTS mode: TMOD Toggle Mode Select 1 = PWM toggle mode TBIT Toggle Bit Initial Value Determines the initial value of TBIT.
Page 141 8XC196NT USER’S MANUAL Start Start Timer Timer Match Match Toggle Output Toggle Output PTS Cycle TBIT TBIT EPA0_TIME = EPA0_TIME + (T2 - T1) EPA0_TIME = EPA0_TIME + (T2 - T1) EPA0_TIME = EPA0_TIME + T1 EPA0_TIME = EPA0_TIME + T1...
Page 142: Pwm Remap Mode Example
STANDARD AND PTS INTERRUPTS When the next timer match occurs, the PTS cycle (Figure 5-17) increments EPA0_TIME by T1 (if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)). (Note that although the values of the EPA0 output and TBIT are the same in this example, these two values are unrelated.
Page 143 8XC196NT USER’S MANUAL Table 5-14. PWM Remap Mode PTSCB PTSCB0 for EPA0 PTSCB1 for EPA1 Unused Unused Unused Unused PTSCONST1 (HI) = T2 (HI) PTSCONST1 (HI) = T2 (HI) PTSCONST1 (LO) = T2 (LO) PTSCONST1 (LO) = T2 (LO) PTSPTR1 (HI) = 1FH (EPA0_TIME, HI)
Page 144 STANDARD AND PTS INTERRUPTS PTS PWM Remap Mode Control Block In PWM remap mode, the PTS uses two EPA channels to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the address pointer (PTSPTR1), and a control register (PTSCON).
Page 145 8XC196NT USER’S MANUAL PTS PWM Remap Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits specify the PTS mode: TMOD Remap Mode Select 0 = PWM remap mode TBIT Toggle Bit Initial Value Determines the initial value of TBIT.
Page 146 STANDARD AND PTS INTERRUPTS Start Start Timer Timer Match Match If EPA0, set the output If EPA0, set the output If EPA1, clear the output If EPA1, clear the output PTS Cycle If EPA0: EPA0_TIME = EPA0_TIME + T2 If EPA0: EPA0_TIME = EPA0_TIME + T2 If EPA1: EPA1_TIME = EPA1_TIME + T2 If EPA1: EPA1_TIME = EPA1_TIME + T2 Toggle TBIT...
Page 148: I/O Ports
I/O Ports...
Page 150: I/O Ports Overview
CHAPTER 6 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surrounding system circuitry. They can read system status, monitor system operation, output device status, configure system options, generate control signals, provide serial communication, and so on. Their usefulness in an application is limited only by the number of I/O pins available and the imagination of the engineer.
Page 151: Standard Input-Only Port Operation
8XC196NT USER’S MANUAL Table 6-2 lists the standard input-only port pins and Table 6-3 describes the P0_PIN status regis- ter. Table 6-2. Standard Input-only Port Pins Special-function Special-function Associated Port Pin Signal(s) Signal Type Peripheral P0.7:0 ACH7:0 Input A/D converter Table 6-3.
Page 152: Standard Input-Only Port Considerations
I/O PORTS 6.2.2 Standard Input-only Port Considerations Port 0 pins are unique in that they may individually be used as digital inputs and analog inputs at the same time. However, reading the port induces noise into the A/D converter, decreasing the accuracy of any conversion in progress.
Page 153 8XC196NT USER’S MANUAL Table 6-4. Bidirectional Port Pins Special-function Special-function Associated Port Pin Signal(s) Signal Type Peripheral EPA0 P1.0 T2CLK Timer 2 P1.1 EPA1 EPA2 P1.2 T2DIR Timer 2 P1.3 EPA3 P1.4 EPA4 P1.5 EPA5 P1.6 EPA6 P1.7 EPA7 P2.0 P2.1...
Page 154: Bidirectional Port Operation
I/O PORTS ter is a status register that returns the logic level present on the pins; it can only be read. The registers for the standard ports are byte-addressable and can be windowed. The port 5 registers must be accessed using 16-bit addressing and cannot be windowed. “Bidirectional Port Consid- erations”...
Page 155 8XC196NT USER’S MANUAL In special-function mode (selected by setting Px_MODE.y), SFDIR and SFDATA are input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance. Special-function output signals clear SFDIR; special-function input sig- nals set SFDIR.
Page 156 I/O PORTS Internal Bus Px_REG SFDATA I/O Pin Px_DIR SFDIR Px_MODE Sample 150Ω to 200Ω Latch Px_PIN Read Port PH1 Clock Medium Pullup 300ns Delay RESET# Weak RESET# Pullup Any Write to Px_MODE A0238-04 Figure 6-2. Bidirectional Port Structure...
Page 157 8XC196NT USER’S MANUAL Table 6-6. Logic Table for Bidirectional Ports in I/O Mode Open-drain Configuration Complementary Output Input Output P x _MODE P x _DIR SFDIR SFDATA P x _REG 0, 1 (Note 2) on, off (Note 2) P x _PIN...
Page 158: Bidirectional Port Pin Configurations
I/O PORTS 6.3.2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I/O pin or as a pin for a special-function signal. In the special-function configuration, the signal is controlled by an on-chip peripheral or an off-chip component. In either configuration, two modes are possible: •...
Page 159: Bidirectional Port Pin Configuration Example
8XC196NT USER’S MANUAL Table 6-8. Control Register Values for Each Configuration Desired Pin Configuration Configuration Register Settings † Standard I/O Signal P x _DIR P x _MODE P x _REG Complementary output, driving 0 Complementary output, driving 1 Open-drain output, strongly driving 0...
Page 160: Bidirectional Port Considerations
I/O PORTS Table 6-10. Port Pin States After Reset and After Example Code Execution † Resulting Pin States Action or Code Px.7 Px.6 Px.5 Px.4 Px.3 Px.2 Px.1 Px.0 Reset LDB P x _DIR, #00011111B LDB P x _MODE, #00000000B LDB P x _REG, #10010011B †...
Page 161 P2.6/HLDA# is the enable pin for ONCE mode (see Chapter 13, “Special Operating Modes”) and one of the enable pins for Intel- reserved test modes. Because a low input during reset could cause the device to enter ONCE mode or a reserved test mode, exercise caution if you use this pin for input.
Page 162 P5.4/SLPINT This pin is weakly held high until your software writes to P5_MODE. P5.4/SLPINT is one of the enable pins for Intel-reserved test modes. Because a low input during reset could cause the device to enter a reserved test mode, exercise caution if you use this pin for input.
Page 163: Design Considerations For External Interrupt Inputs
8XC196NT USER’S MANUAL 6.3.5 Design Considerations for External Interrupt Inputs To configure a port pin that serves as an external interrupt input, you must set the corresponding bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). To configure P2.2/EX- TINT as an external interrupt input, we recommend the following sequence to prevent a false in- terrupt request: Disable interrupts by executing the DI instruction.
Page 164: Bidirectional Ports 3 And 4 (Address/Data Bus) Operation
I/O PORTS Table 6-11. Ports 3 and 4 Pins Special-function Special-function Port Pins Associated Peripheral Signal(s) Signal Type AD7:0 Address/data bus, low byte P3.7:0 PBUS7:0 Programming bus, low byte SLP7:0 Slave port AD15:8 Address/data bus, high byte P4.7:0 PBUS15:8 Programming bus, high byte Table 6-12.
Page 165 8XC196NT USER’S MANUAL Internal Bus Px_REG ADDRESS/DATA I/O Pin BUS CONTROL SELECT 0=Address/Data 1=I/O P34_DRV RESET# Sample 150Ω to 200Ω Latch Px_PIN Buffer Read Port PH1 Clock Medium Pullup 300ns Delay RESET# Weak Pullup A0240-03 Figure 6-3. Address/Data Bus (Ports 3 and 4) Structure When external memory access is not required, the device sets BUS CONTROL SELECT, select- ing Px_REG as the input to the multiplexer.
Page 166: Using Ports 3 And 4 As I/O
I/O PORTS With the open-drain configuration (BUS CONTROL SELECT set and P34_DRV cleared) and Px_REG set, the pin can be used as an input. The signal on the pin is latched in the Px_PIN reg- ister. The pins can be read, making it easy to see which pins are driven low by the device and which are driven high by external drivers while in open-drain mode.
Page 167: Design Considerations For Ports 3 And 4
8XC196NT USER’S MANUAL 6.4.3 Design Considerations for Ports 3 and 4 When EA# is active, ports 3 and 4 will function only as the address/data bus. In these circum- stances, an instruction that operates on P3_REG or P4_REG causes a bus cycle that reads from or writes to the external memory location corresponding to the SFR’s address.
Page 168: Eport Operation
I/O PORTS Table 6-15. EPORT Control and Status Registers (Continued) Mnemonic Address Description EP_MODE 1FE1H EPORT Mode Each bit of EP_MODE controls whether the corresponding pin functions as a standard I/O port pin or as an extended-address signal. Setting a bit configures a pin as an extended-address signal; clearing a bit configures a pin as a standard I/O port pin.
Page 169 8XC196NT USER’S MANUAL Internal Bus I/O MUX EP_REG Address MUX Data CODE Extended Code Address (from CPU) EDAR DATA I/O Pin Extended Data Address (from CPU) Combinational Logic Data/Address Control (from Bus Controller) MODE64 Control (from CPU) Mode EP_MODE EP_DIR...
Page 170: Reset
I/O PORTS Figure 6-5 shows a circuit schematic for a single bit of the EPORT. Q1 and Q2 are the strong com- plementary drivers for the pin. Q1 can source at least –3 mA at V – 0.7 volts. Q2 can sink at least 3 mA at 0.45 volts.
Page 171 8XC196NT USER’S MANUAL Internal Bus RESET# EP_REG DATA Address Bit from Address MUX I/O Pin EP_MODE EP_DIR POWERDOWN# IDLE# HOLD# Sample Latch 150Ω to 200Ω EP_PIN Buffer Read Port PH1 Clock Medium Pullup 300ns Delay RESET# Weak Pullup A0241-02 Figure 6-5. EPORT Structure...
Page 172: Input Mode
I/O PORTS 6.5.1.5 Input Mode Input mode is obtained by configuring the pin as an open-drain output (EP_DIR set and EP_MODE clear) and writing a one to EP_REG.x. In this configuration, Q1 and Q2 are both off, allowing an external device to drive the pin. To determine the value of the I/O pin, read EP_PIN.x. Table 6-16 is a logic table for I/O operation and Table 6-17 is a logic table for address mode op- eration of EPORT.
Page 173: Configuring Eport Pins
8XC196NT USER’S MANUAL 6.5.2 Configuring EPORT Pins Each EPORT pin can be individually configured to operate either as an extended-address signal or as an I/O pin in one of these modes: • complementary output (output only) • high-impedance input or open-drain output (input, output, or bidirectional) 6.5.2.1...
Page 174: Eport Considerations
I/O PORTS 6.5.3 EPORT Considerations This section outlines considerations for using the EPORT pins. 6.5.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold During reset, the EPORT pins are forced to their extended-address functions and are weakly pulled high. During the CCB fetch, FFH is strongly driven onto the pins. This value remains strongly driven until either the pin is configured for I/O or a different extended address is access- ed.
Page 175: Eport Status During Instruction Execution
8XC196NT USER’S MANUAL 6.5.3.3 EPORT Status During Instruction Execution When using the EPORT to address memory outside page 00H, keep these points in mind: During extended accesses, the upper four bits of the address (lower four bits of the EPC) are sent to the EPORT.
Page 176: Serial I/O (Sio) Port
Serial I/O (SIO) Port...
Page 178: Serial I/O (Sio) Port Functional Overview
CHAPTER 7 SERIAL I/O (SIO) PORT A serial input/output (SIO) port provides a means for the system to communicate with external devices. This device has a serial I/O (SIO) port that shares pins with port 2. This chapter describes the SIO port and explains how to configure it. Chapter 6, “I/O Ports,” explains how to configure the port pins for their special functions.
Page 179: Serial I/O Port Signals And Registers
8XC196NT USER’S MANUAL SERIAL I/O PORT SIGNALS AND REGISTERS Table 7-1 describes the SIO signals and Table 7-2 describes the control and status registers. Table 7-1. Serial Port Signals Serial Port Serial Port Port Description Signal Signal Type P2.0 Transmit Serial Data In modes 1, 2, and 3, TXD transmits serial port output data.
Page 180 SERIAL I/O (SIO) PORT Table 7-2. Serial Port Control and Status Registers (Continued) Mnemonic Address Description P2_REG 1FCDH Port 2 Output Data This register holds data to be driven out on the pins of port 2. Set P2_REG.1 for the RXD (P2.1) pin. Write the desired output data for the TXD (P2.0) pin to P2_REG.0.
Page 181: Serial Port Modes
8XC196NT USER’S MANUAL SERIAL PORT MODES The serial port has both synchronous and asynchronous operating modes for transmission and re- ception. This section describes the operation of each mode. 7.3.1 Synchronous Mode (Mode 0) The most common use of mode 0, the synchronous mode, is to expand the I/O capability of the device with shift registers (see Figure 7-2).
Page 182: Asynchronous Modes (Modes 1, 2, And 3)
SERIAL I/O (SIO) PORT During a reception, the RI flag in SP_STATUS is set after the stop bit is sampled. The RI pending bit in the interrupt pending register is set immediately before the RI flag is set. During a transmis- sion, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted.
Page 183: Mode 2
8XC196NT USER’S MANUAL Stop Start Stop 8 Bits of Data or 7 Bits of Data with Parity Bit 10-Bit Frame A0245-02 Figure 7-4. Serial Port Frames for Mode 1 The transmit and receive functions are controlled by separate shift clocks. The transmit shift clock starts when the baud rate generator is initialized.
Page 184: Mode 3
SERIAL I/O (SIO) PORT Stop Stop Start 8 Bits of Data Programmable 9th Bit 11-Bit Frame A0111-01 Figure 7-5. Serial Port Frames in Mode 2 and 3 7.3.2.3 Mode 3 Mode 3 is the asynchronous, ninth-bit mode. The data frame for this mode is identical to that of mode 2.
Page 185: Programming The Serial Port
8XC196NT USER’S MANUAL PROGRAMMING THE SERIAL PORT To use the SIO port, you must configure the port pins to serve as special-function signals and set up the SIO channel. 7.4.1 Configuring the Serial Port Pins Before you can use the serial port, you must configure the associated port pins to serve as special- function signals.
Page 186 SERIAL I/O (SIO) PORT Address: 1FBBH SP_CON Reset State: The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. — — Function Number Mnemonic — Reserved; always write as zeros. Parity Selection Bit Selects even or odd parity.
Page 187 8XC196NT USER’S MANUAL Address: 1FBCH SP_BAUD Reset State: 0000H The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.
Page 188: Enabling The Serial Port Interrupts
SERIAL I/O (SIO) PORT The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXD. Although these two signals are normally synchronized, the internal signal generates one clock before the first pulse transmitted by TXD and this first clock signal is not synchronized with TXD.
Page 189: Determining Serial Port Status
8XC196NT USER’S MANUAL 7.4.5 Determining Serial Port Status You can read the SP_STATUS register (Figure 7-8) to determine the status of the serial port. Reading SP_STATUS clears all bits except TXE. For this reason, we recommend that you copy the contents of the SP_STATUS register into a shadow register and then execute bit-test instruc- tions such as JBC and JBS on the shadow register.
Page 190: Programming Example Using An Interrupt-Driven Routine
SERIAL I/O (SIO) PORT The receiver checks for a valid stop bit. Unless a stop bit is found within the appropriate time, the framing error (FE) bit in the SP_STATUS register is set. When the stop bit is detected, the data in the receive shift register is loaded into SBUF_RX and the receive interrupt (RI) flag is set.
Page 191 8XC196NT USER’S MANUAL #define TRANSMIT_BUF_SIZE 20 #define RECEIVE_BUF_SIZE 20 #define WINDOW_SELECT 0x1F #define FREQUENCY (long)16000000 /* 16 MHz #define BAUD_RATE_VALUE 9600 #define BAUD_REG ((unsigned int)(FREQUENCY/((long)BAUD_RATE_VALUE*16)-1)+0x8000) #define RI_BIT 0x40 #define TI_BIT 0x20 unsigned char status_temp; image of SP_STATUS to preserve the RI and TI bits on a read.
Page 192 SERIAL I/O (SIO) PORT void receive(void) serial interrupt routine wsr = WINDOW_SELECT; status_temp |= SP_STATUS; image SP_STATUS into status_temp If the input buffer is full, the last character will be ignored, and the BEL character is output to the terminal. if(end_rec_buff+1==begin_rec_buff || (end_rec_buff==RECEIVE_BUF_SIZE-1 &&...
Page 193 8XC196NT USER’S MANUAL port2_reg 0xFF; Init port2 reg */ port2_dir &= 0xFE; TXD output port2_mode |= 0x03; p2.4-6 lsio wsr=0; end_rec_buff=0; /* initialize buffer pointers begin_rec_buff=0; end_trans_buff=0; begin_trans_buff=0; status_temp = TI_BIT; /* allow for initial transmission int_mask1=0x18; /* enable the serial port interrupt enable();...
Page 194: Synchronous Serial I/O (Ssio) Port
Synchronous Serial I/O (SSIO) Port...
Page 196: Synchronous Serial I/O (Ssio) Port Functional Overview
CHAPTER 8 SYNCHRONOUS SERIAL I/O (SSIO) PORT This device has a synchronous serial I/O (SSIO) port that shares pins with port 6. This chapter describes the SSIO port and explains how to program it. Chapter 6, “I/O Ports,” explains how to configure the port pins for their special functions.
Page 197: Ssio Port Signals And Registers
8XC196NT USER’S MANUAL SSIO PORT SIGNALS AND REGISTERS Table 8-1 describes the SSIO signals and Table 8-2 describes the control and status registers. Table 8-1. SSIO Port Signals SSIO Port SSIO Port Port Description Signal Type Signal P6.4 SSIO0 Clock Pin...
Page 198: Ssio Operation
SYNCHRONOUS SERIAL I/O (SSIO) PORT Table 8-2. SSIO Port Control and Status Registers (Continued) Mnemonic Address Description INT_PEND1 0012H Interrupt Pending 1 When set, SSIO0 indicates a pending channel 0 transfer interrupt. When set, SSIO1 indicates a pending channel 1 transfer interrupt. P6_DIR 1FD2H Port 6 Direction...
Page 199 8XC196NT USER’S MANUAL Master Slave Single-channel Half-duplex Master/Slave Configuration Master Slave Slave Slave Double-channel Full-duplex Lockstep Common Clock Configuration Master Slave Slave Master Double-channel Full-duplex Master/Slave Separate Clock Configuration A0233-03 Figure 8-2. SSIO Operating Modes • One channel can act as master transceiver to communicate with compatible protocols in half-duplex mode.
Page 200 SYNCHRONOUS SERIAL I/O (SSIO) PORT • The two channels can operate together, from the same clock, as master transceivers to communicate in lockstep (mutually synchronous), full-duplex mode. This mode requires one data input pin, one data output pin, and two clock pins (the clock output pin from one channel connected to the clock input pin of the other).
Page 201: Ssio Handshaking
8XC196NT USER’S MANUAL SC x SD x (out) SD x (in) valid valid valid valid valid valid valid valid SC x (Handshake Mode) Slave Receiver Pulls SC x low A0266-01 Figure 8-3. SSIO Transmit/Receive Timings SSIO HANDSHAKING Handshaking (Figure 8-4) prevents a data underflow or overflow from occurring at the slave, which enables a master device to perform SSIO data transfers using the PTS.
Page 202: Ssio Handshaking Operation
SYNCHRONOUS SERIAL I/O (SSIO) PORT Load SSIO x _BUF Receive Byte Pull SC Pin Low SC x Pin High SSIO x _BUF Read Transmit Byte Set SSIO x Interrupt Float SC x Pin Pending Bit SSIO Transmit Handshaking SSIO Receive Handshaking A0232-03 Figure 8-4.
Page 203 8XC196NT USER’S MANUAL The following example describes how the master can transmit 16 bytes of data to the slave through the PTS, using this optional handshaking capability. These four steps can occur in any order: — You initialize the master as a transmitter and the slave as a receiver.
Page 204: Programming The Ssio Port
SYNCHRONOUS SERIAL I/O (SSIO) PORT PROGRAMMING THE SSIO PORT To use the SSIO port, you must configure the port pins to serve as special-function signals, then set up the SSIO channels. 8.5.1 Configuring the SSIO Port Pins Before you can use the SSIO port, you must configure the necessary port 6 pins to serve as their special-function signals.
Page 205 8XC196NT USER’S MANUAL Address: 1FB4H SSIO_BAUD Reset State: The synchronous serial port baud (SSIO_BAUD) register enables and disables the baud-rate generator and selects the SSIO baud rate. During read operations, SSIO_BAUD serves as the down- counter monitor. The down-counter is decremented once every four state times when the baud-rate generator is enabled.
Page 206: Controlling The Communications Mode And Handshaking
SYNCHRONOUS SERIAL I/O (SSIO) PORT 8.5.3 Controlling the Communications Mode and Handshaking The SSIOx_CON register (Figure 8-6) controls the communications mode and handshaking. The two least-significant bits indicate whether an underflow or overflow has occurred and whether the channel is ready to transmit or receive. Address: 1FB1H, 1FB3H SSIO x _CON...
Page 207 8XC196NT USER’S MANUAL Address: 1FB1H, 1FB3H SSIO x _CON (Continued) Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 208: Enabling The Ssio Interrupts
SYNCHRONOUS SERIAL I/O (SSIO) PORT 8.5.4 Enabling the SSIO Interrupts Each SSIO channel can generate an interrupt request if you enable the individual interrupt as well as globally enabling servicing of all maskable interrupts. The INT_MASK1 register enables and disables individual interrupts. To enable an SSIO interrupt, set the corresponding bit in INT_MASK1 (see Table 8-2 on page 8-2) and execute the EI instruction to globally enable inter- rupt servicing.
Page 209 8XC196NT USER’S MANUAL Clock (SC x pin) "1" "0" "1" "0" "0" Data (SD x pin) A2066-01 Figure 8-7. Variable-width MSB in SSIO Transmissions NOTE This condition exists only for the MSB. Once the MSB is clocked out, the remaining bits are clocked out consistently at the programmed frequency.
Page 210: Programming Example
SYNCHRONOUS SERIAL I/O (SSIO) PORT PROGRAMMING EXAMPLE This code example configures SSIO0 as a master transmitter to send one byte of data to SSIO1, the slave receiver. First it sets up a window to allow direct access to the necessary registers. Next, it configures the clock and data pins.
Page 212: Slave Port
Slave Port...
Page 214 DPRAM on-chip, inside the microcontroller (Figure 9-1). With this configuration, the exter- nal processor (master) can simply read from and write to the on-chip memory of the 8XC196NT (slave) processor. The slave port requires more pins than a serial link does, but fewer than the number used for a parallel bus.
Page 215: Slave Port Functional Overview
8-bit address/data bus (SLP7:0). The slave 8XC196NT processor communicates with the master (the external device) through the slave port registers. From the slave viewpoint, the status register and data output register are output-only registers that are latched onto the slave port address/data bus when SLPCS# and SLPRD# are both low.
Page 216 SLAVE PORT SLP_STAT.0 SLPINT/ P5.4 SLP_STAT.1 SLPALE /P5.0 SLP_CON.2 SLP_CON SLP_ADDR SLP1/P3.1 SLPRD# /P5.3 SLPWR# /P5.2 SLP_STAT SLPCS# P3_REG P5.1 (Data Out) P3_PIN (Data In) SLP7:0/ SLP_CMD P3.7:0 Internal 8XC196 Device A0267-03 Figure 9-2. Slave Port Block Diagram...
Page 217 8XC196NT USER’S MANUAL Table 9-1. Slave Port Signals Slave Slave Port Port Pin Port Description Signal Type Signal P3.7:0 SLP7:0 Slave Port Address/Data bus Slave port address/data bus in multiplexed mode and slave port data bus in demultiplexed mode. In multiplexed mode, SLP1 is the source of the internal control signal, SLP_ADDR.
Page 218 SLAVE PORT Table 9-2. Slave Port Control and Status Registers (Continued) Mnemonic Address Description INT_PEND1 0012H Interrupt Pending 1 Bit 0, when set, indicates a pending command buffer full (CBF) interrupt. This bit is set after the master writes to the command register, SLP_CMD.
Page 219: Hardware Connections
8XC196NT USER’S MANUAL HARDWARE CONNECTIONS Figure 9-3 shows the basic hardware connections for both multiplexed and demultiplexed bus modes. Table 9-3 lists the interconnections. Note that the shared memory mode supports only a multiplexed bus, while the standard slave mode supports either a multiplexed or a demultiplexed bus.
Page 220 SLAVE PORT Slave Interrupt Output SLPINT Data Read (RD#) SLPRD# Data Write (WR#) SLPWR# Address Latch Enable (ALE) SLPALE Latched Address Decoder Chip Select (CS#) SLPCS# Master Processor SLP7:0 Address/Data Bus or System Bus 8XC196 Slave Processor Slave Port Connections for Multiplexed Bus Interface Slave Interrupt Output SLPINT Data Read (RD#)
Page 221: Slave Port Modes
8XC196NT USER’S MANUAL SLAVE PORT MODES The slave port can operate in either standard slave mode or shared memory mode. In both modes, the master and slave share a 256-byte block of memory located anywhere within the slave’s mem- ory space. Data written is stored in the slave’s P3_PIN register; data to be read is stored in the slave’s P3_REG register.
Page 222: Slave Device Program
SLAVE PORT The master first reads the P3_REG register. This ensures that the slave’s P3_REG is indeed emp- ty, clears the OBF flag, and pulls SLPINT low. Next, it loads the address it wants to read into the SLP_CMD register. This causes a CBF interrupt in the slave processor. The slave reads that lo- cation and stores the data in P3_REG, which sets the OBF flag and forces SLPINT high.
Page 223: Demultiplexed Bus Timings
8XC196NT USER’S MANUAL READ_DATA: TEMPW, [MAILBOX] ; get data to write to P3_REG TEMPW, P3_REG[0] ; write SLP_CMD+400H data to P3_REG POPA 9.4.1.3 Demultiplexed Bus Timings The master processor performs two bus cycles for each byte written and three bus cycles for each byte read.
Page 224: Shared Memory Mode Example
SLAVE PORT 9.4.2 Shared Memory Mode Example In shared memory mode, the master and slave share a 256-byte block of memory. The high byte of the address (the base address) controls the location within the slave device memory space. The low byte of the address is always in the SLP_CMD register.
Page 225: Slave Device Program
8XC196NT USER’S MANUAL 9.4.2.2 Slave Device Program This example shows how the slave device reacts to reads and writes requested by the master. Re- gardless of the operation to be performed, the address is latched into the SLP_CMD register. The interrupt determines whether a read or write operation is to be performed.
Page 226: Multiplexed Bus Timings
SLAVE PORT 9.4.2.3 Multiplexed Bus Timings The memory space required for the sample code is four bytes (two bytes for the address register, one for the temp register, and one for the base address). Reads and writes each require 58 state times (5.8 µs at 20 MHz).
Page 227: Configuring The Slave Port
8XC196NT USER’S MANUAL CONFIGURING THE SLAVE PORT Before you can use the slave port, you must configure the associated port 3 and port 5 pins to serve as special-function signals. (See Chapter 6, “I/O Ports,” for configuration details.) • Configure P5.3:0 as special-function inputs.
Page 228 SLAVE PORT Address: 1FFBH SLP_CON Reset State: The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can access the register. — — — SLPL IBEMSK OBFMSK Function Number Mnemonic — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits.
Page 229: Enabling The Slave Port Interrupts
8XC196NT USER’S MANUAL 9.5.2 Enabling the Slave Port Interrupts The master can generate three interrupt requests: command buffer full (CBF), output buffer emp- ty (OBE), and input buffer full (IBF). The CBF interrupt is used in standard slave mode; the OBE and IBF interrupts are used in shared memory mode.
Page 230 SLAVE PORT Address: 1FF8H SLP_STAT Reset State: The master can read the slave port status (SLP_STAT) register to determine the status of the slave. The slave can read all bits and can write bits 7:3 for general-purpose status information. (The bits are user-defined flags.) If the master attempts to write to SLP_STAT, it actually writes to SLP_CMD.
Page 232: Event Processor Array (Epa)
Event Processor Array (EPA)
Page 234: Epa Functional Overview
CHAPTER 10 EVENT PROCESSOR ARRAY (EPA) Control applications often require high-speed event control. For example, the controller may need to periodically generate pulse-width modulated outputs, an analog-to-digital conversion, or an in- terrupt. In another application, the controller may monitor an input signal to determine the status of an external device.
Page 235: Epa And Timer/Counter Signals And Registers
8XC196NT USER’S MANUAL Timer-Counter Unit TIMER1 TIMER2 Capture/Compare EPA 3:0 Interrupts Channel 0–3 EPA 3:0 Capture/Compare Channel 4–7 EPA7:4 Capture/Compare EPA8 / COMP0 Channel 8 EPA x Interrupt Indirect Compare-only Interrupt Channel 0 Processor Logic Capture/Compare Channel 9 EPA9 / COMP1...
Page 236 EVENT PROCESSOR ARRAY (EPA) Table 10-1. EPA and Timer/Counter Signals Port Pin EPA Signal(s) Description Signal Type P1.0 EPA0 High-speed input/output for capture/compare channel 0. T2CLK External clock source for timer 2. If you use T2CLK, you cannot use capture/compare channel P1.1 EPA1 High-speed input/output for capture/compare...
Page 237 8XC196NT USER’S MANUAL Table 10-2. EPA Control and Status Registers (Continued) Mnemonic Address Description EPA0_CON 1F60H EPA x Capture/Compare Control EPA1_CON 1F64H These registers control the functions of the capture/compare EPA2_CON 1F68H channels. EPA1_CON and EPA3_CON require an extra byte...
Page 238 EVENT PROCESSOR ARRAY (EPA) Table 10-2. EPA Control and Status Registers (Continued) Mnemonic Address Description P1_REG 1FD4H Port x Data Output P6_REG 1FD5H For an input, set the corresponding P x _REG bit. For an output, write the data to be driven out by each pin to the corresponding bit of P x _REG.
Page 239: Timer/Counter Functional Overview
8XC196NT USER’S MANUAL 10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW The EPA has two 16-bit up/down timer/counters, timer 1 and timer 2, which can be clocked in- ternally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked externally.
Page 240: Cascade Mode (Timer 2 Only)
EVENT PROCESSOR ARRAY (EPA) The timer/counters can be used as time bases for input captures, output compares, and pro- grammed interrupts (software timers). When a counter increments from FFFEH to FFFFH or dec- rements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can optionally cause an interrupt.
Page 241 8XC196NT USER’S MANUAL Increment 8XC196 Device Decrement T x CLK X_internal Optical Reader T x DIR Y_internal A0268-02 Figure 10-3. Quadrature Mode Interface Table 10-3. Quadrature Mode Truth Table State of X_internal State of Y_internal Count Direction (T x CLK) (T x DIR) ↑...
Page 242: Epa Channel Functional Overview
EVENT PROCESSOR ARRAY (EPA) CLKOUT T x CLK T x DIR COUNT x + 1 x + 2 x + 3 x + 4 x + 5 x + 6 x + 5 x + 4 x + 3 x + 2 x + 1 A0269-02 Figure 10-4.
Page 243 8XC196NT USER’S MANUAL Each EPA channel has a control register, EPAx_CON (capture/compare channels) or COMPx_CON (compare-only channels); an event-time register, EPAx_TIME (capture/compare channels) or COMPx_TIME (compare-only channels); and a timer input (Figure 10-5). The con- trol register selects the timer, the mode, and either the event to be captured or the event that is to occur.
Page 244: Operating In Capture Mode
EVENT PROCESSOR ARRAY (EPA) 10.4.1 Operating in Capture Mode In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register, which sets the EPA interrupt pending bit as shown in Figure 10-6.
Page 245: Handling Epa Overruns
8XC196NT USER’S MANUAL Event 1 2 State 2 State Times Times Event 2 2 State 2 State Times Times A3130-01 Figure 10-7. Valid EPA Input Events Table 10-4. Action Taken when a Valid Edge Occurs Status of Overwrite Bit Capture Buffer Action taken when a valid edge occurs (EPA x _CON.0)
Page 246: Operating In Compare Mode
EVENT PROCESSOR ARRAY (EPA) The input frequency at which this occurs depends on the length of the interrupt service routine as well as other factors. Unless the interrupt service routine includes a check for overruns, this situ- ation will remain the same until the device is reset or the EPAx_TIME register is read. The act of reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME.
Page 247: Generating A Low-Speed Pwm Output
8XC196NT USER’S MANUAL 10.4.2.1 Generating a Low-speed PWM Output You can generate a low-speed, pulse-width modulated output with a single EPA channel and a standard interrupt service routine. Configure the EPA channel as follows: compare mode, toggle output, and the compare function re-enabled. Select standard interrupt service, enable the EPA interrupt, and globally enable interrupts with the EI instruction.
Page 248: Generating A Medium-Speed Pwm Output
EVENT PROCESSOR ARRAY (EPA) The worst-case interrupt latency for a single-interrupt system is 56 state times for external stack usage and 54 state times for internal stack usage (see “Standard Interrupt Latency” on page 5-9). To determine the execution time for an interrupt service routine, add up the execution time of the instructions in the ISR (Table A-9).
Page 249: Generating A High-Speed Pwm Output
8XC196NT USER’S MANUAL The worst-case interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Interrupt Latency” on page 5-9). The PTS cycle execution time in PWM toggle mode is 15 state times (Table 5-4 on page 5-10). Therefore, a single capture/compare channel 0–3 can be updated every 58 state times (43 + 15).
Page 250: Programming The Epa And Timer/Counters
EVENT PROCESSOR ARRAY (EPA) With this method, the resolution of the EPA (selected by the TxCONTROL registers; see Figure 10-8 on page 10-18 and Figure 10-9 on page 10-19) determines the maximum PWM output fre- quency. (Resolution is the minimum time required between a capture or compare.) At 20 MHz, a 200 ns resolution results in a maximum PWM of 5 MHz.
Page 251 8XC196NT USER’S MANUAL Address: 1F98H T1CONTROL Reset State: The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 252 EVENT PROCESSOR ARRAY (EPA) Address: 1F9CH T2CONTROL Reset State: The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 253: Programming The Capture/Compare Channels
8XC196NT USER’S MANUAL 10.5.3 Programming the Capture/Compare Channels The EPAx_CON register controls the function of its assigned capture/compare channel. The reg- isters for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an ad- ditional bit, the remap bit (RM), which is used to enable and disable remapping for high-speed PWM generation (see “Generating a High-speed PWM Output”...
Page 254 EVENT PROCESSOR ARRAY (EPA) Address: See Table 10-2 on EPA x _CON page 10-3 x = 0–9 Reset State: F700H ( x = 1 & 3) 00H( x = 0, 2, 4–9) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 255 8XC196NT USER’S MANUAL Address: See Table 10-2 on EPA x _CON (Continued) page 10-3 x = 0–9 Reset State: F700H ( x = 1 & 3) 00H( x = 0, 2, 4–9) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 256 EVENT PROCESSOR ARRAY (EPA) Address: See Table 10-2 on EPA x _CON (Continued) page 10-3 x = 0–9 Reset State: F700H ( x = 1 & 3) 00H( x = 0, 2, 4–9) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 257 8XC196NT USER’S MANUAL Address: See Table 10-2 on EPA x _CON (Continued) page 10-3 x = 0–9 Reset State: F700H ( x = 1 & 3) 00H( x = 0, 2, 4–9) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 258: Programming The Compare-Only Channels
EVENT PROCESSOR ARRAY (EPA) 10.5.4 Programming the Compare-only Channels To program a compare event, you must first write to the COMPx_CON (Figure 10-11) register to configure the compare-only channel and then load the event time into COMPx_TIME. COMPx_CON has the same bits and settings as EPAx_CON. COMPx_TIME is functionally iden- tical to EPAx_TIME.
Page 259: Enabling The Epa Interrupts
8XC196NT USER’S MANUAL Address: 1F88H ( x = 0) COMP x _CON 1F8CH ( x = 1) (Continued) Reset State: x = 0–1 The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels. Function...
Page 260: Determining Event Status
EVENT PROCESSOR ARRAY (EPA) Address: 1FA0H EPA_MASK Reset State: 0000H The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the multiplexed EPA x interrupt EPA4 EPA5 EPA6 EPA7 EPA8 EPA9 OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVR8...
Page 261 8XC196NT USER’S MANUAL The EPA0–EPA3 pending bits are located in INT_PEND (Figure 5-7 on page 5-17). The pending bits for the multiplexed interrupts (those that share EPAx) are located in EPA_PEND (Figure 10-14) and EPA_PEND1 (Figure 10-15). If an interrupt is masked, software can still poll the in- terrupt pending registers to determine whether an event has occurred.
Page 262: Servicing The Multiplexed Epa Interrupt With Software
EVENT PROCESSOR ARRAY (EPA) 10.8 SERVICING THE MULTIPLEXED EPA INTERRUPT WITH SOFTWARE The multiplexed interrupts (those represented by EPAx) should be serviced with a standard inter- rupt service routine rather than the PTS (Chapter 5, “Standard and PTS Interrupts”). The PTS can take only a limited number of actions, while interrupt service routines can be tailored to the needs of each interrupt.
Page 263 8XC196NT USER’S MANUAL Address: 1FA8H EPAIPV Reset State: When an EPA x interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table 10-6). EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine when EPA x is activated.
Page 264: Using The Tijmp Instruction To Reduce Interrupt Service Overhead
EVENT PROCESSOR ARRAY (EPA) 10.8.1 Using the TIJMP Instruction to Reduce Interrupt Service Overhead The EPAIPV register and the TIJMP instruction can be used together to reduce the interrupt ser- vice overhead. The primary purpose of the TIJMP instruction is to reduce the interrupt response time associated with servicing multiplexed interrupts.
Page 265 8XC196NT USER’S MANUAL INIT_INTERRUPTS: JTBASE_PTR,#LSW JTBASE ;store jump table base address EPAx_ISR: EPAIPV_PTR,#EPAIPV ;read EPAIPV offset PUSHA ;save INT_MASK/INT_MASK1/WSR/PSW TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH ;initiate jump to correct ISR OVR_EPA0_ISR: ;EPA0 overrun routine TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH ;check for pending ;interrupts, exit EPAx_DONE: POPA ;exit, all EPAx ;interrupts serviced...
Page 266: Programming Examples For Epa Channels
Intel Literature Fulfillment or the Intel Applications Bulletin Board system (BBS). See Chapter 1, “Guide to This Manual,” for information about ordering information from Intel Literature and downloading files from the BBS. These sample program were written in the C programming lan- guage.
Page 267: Epa Capture Event Program
8XC196NT USER’S MANUAL void poll_epa0() if(checkbit(int_pend, EPA0_INT_BIT)) User code for event channel 0 would go here. */ Since this event is absolute and re-enabled, no polling is neccessary.*/ clrbit(int_pend, EPA0_INT_BIT); void main(void) /* Initialize the timers before using the epa */ init_timer1();...
Page 268: Epa Pwm Output Program
EVENT PROCESSOR ARRAY (EPA) time_value = epa0_time; /* must read to prevent overrun */ /* To generate have code for the epax interrupt,select the ICU design screen.*/ void init_timer1() t1control = COUNT_ENABLE | COUNT_UP | CLOCK_INTERNAL | DIVIDE_BY_1; void main(void) unsigned int time_value;...
Page 269 8XC196NT USER’S MANUAL /* Sample PTS control block initialization sequence.*/ void Init_PWM_toggle_PTS3(void) disable(); /* disable all interrupts */ disable_pts(); /* disable the PTS interrupts */ PWM_toggle_CB_3.constant2 = 127; PWM_toggle_CB_3.constant1 = 127; PWM_toggle_CB_3.pts_ptr = (void *)&EPA0_TIME; PWM_toggle_CB_3.ptscon = 0x42; /* Sample code that could be used to generate a PWM with an EPA channel.*/ setbit(p1_reg, 0x1);...
Page 270: Analog-To-Digital Converter
Analog-to-digital Converter...
Page 272: A/D Converter Functional Overview
CHAPTER 11 ANALOG-TO-DIGITAL CONVERTER The analog-to-digital (A/D) converter can convert an analog input voltage to a digital value and set the A/D interrupt pending bit when it stores the result. It can also monitor a pin and set the A/D interrupt pending bit when the input voltage crosses over or under a programmed threshold voltage.
Page 273: A/D Converter Signals And Registers
8XC196NT USER’S MANUAL 11.2 A/D CONVERTER SIGNALS AND REGISTERS Table 11-1 lists the A/D signals and Table 11-2 describes the control and status registers. Al- though the analog inputs are multiplexed with I/O port pins, no configuration is necessary. Table 11-1. A/D Converter Pins...
Page 274: A/D Converter Operation
ANALOG-TO-DIGITAL CONVERTER Table 11-2. A/D Control and Status Registers (Continued) Mnemonic Address Description P0_PIN 1FDAH Port 0 Pin State Read P0_PIN to determine the current values of the port 0 pins. Reading the port induces noise into the A/D converter, decreasing the accuracy of any conversion in progress.
Page 275: Programming The A/D Converter
8XC196NT USER’S MANUAL The A/D converter uses a successive approximation algorithm to perform the analog-to-digital conversion. The converter hardware consists of a 256-resistor ladder, a comparator, coupling ca- pacitors, and a 10-bit successive approximation register (SAR) with logic that guides the process.
Page 276: Programming The A/D Test Register
ANALOG-TO-DIGITAL CONVERTER 11.4.1 Programming the A/D Test Register The AD_TEST register (Figure 11-2) selects either an analog input or a test voltage (ANGND or ) for conversion and specifies an offset voltage to be applied to the resistor ladder. To use the zero-offset adjustment, first perform two conversions, one on ANGND and one on V .
Page 277: Programming The A/D Result Register (For Threshold Detection Only)
8XC196NT USER’S MANUAL 11.4.2 Programming the A/D Result Register (for Threshold Detection Only) To use the threshold-detection modes, you must first write a value to the high byte of AD_RESULT to set the desired reference (threshold) voltage. Address: 1FAAH AD_RESULT (Write)
Page 278 ANALOG-TO-DIGITAL CONVERTER The AD_TIME register (Figure 11-4) specifies the A/D sample and conversion times. To avoid erroneous conversion results, use the T and T specifications on the datasheet to determine CONV appropriate values. Address: 1FAFH AD_TIME Reset State: The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit.
Page 279: Programming The A/D Command Register
0 = EPA initiates conversion ACH2:0 A/D Channel Selection Write the A/D conversion channel number to these bits. The 8XC196NT has four A/D channel inputs, numbered 4–7. NOTES: While a threshold-detection mode is selected for an analog input pin, no other conversion can be started.
Page 280: Enabling The A/D Interrupt
ANALOG-TO-DIGITAL CONVERTER 11.4.5 Enabling the A/D Interrupt The A/D converter can set the A/D interrupt pending bit when it completes a conversion or when the input voltage crosses the threshold value in the selected direction. To enable the interrupt, set the corresponding mask bit in the interrupt mask register (see Table 11-2 on page 11-2) and exe- cute the EI instruction to globally enable servicing of interrupts.
Page 281: Design Considerations
ACH2:0 A/D Channel Number These bits indicate the A/D channel number that was used for the conversion. The 8XC196NT has four A/D channel inputs, numbered 4–7 Figure 11-6. A/D Result (AD_RESULT) Register — Read Format 11.6 DESIGN CONSIDERATIONS This section describes considerations for the external interface circuitry and describes the errors that can occur in any A/D converter.
Page 282: Designing External Interface Circuitry
ANALOG-TO-DIGITAL CONVERTER 11.6.1 Designing External Interface Circuitry The external interface circuitry to an analog input is highly dependent upon the application and can affect the converter characteristics. Factors such as input pin leakage, sample capacitor size, and multiplexer series resistance from the input pin to the sample capacitor must be considered in the external circuit’s design.
Page 283: Minimizing The Effect Of High Input Source Resistance
8XC196NT USER’S MANUAL 11.6.1.1 Minimizing the Effect of High Input Source Resistance Under some conditions, the input source resistance (R ) can be great enough to affect the SOURCE measurement. You can minimize this effect by increasing the sample time or by connecting an external capacitor (C ) from the input pin to ANGND.
Page 284: Suggested A/D Input Circuit
ANALOG-TO-DIGITAL CONVERTER 11.6.1.2 Suggested A/D Input Circuit The suggested A/D input circuit shown in Figure 11-8 provides limited protection against over- voltage conditions on the analog input. Should the input voltage be driven significantly below ANGND or above V , diode D2 or D1 will forward bias at about 0.8 volts. The device’s input protection begins to turn on at approximately 0.5 volts beyond ANGND or V .
Page 285: Using Mixed Analog And Digital Inputs
8XC196NT USER’S MANUAL ANGND should be within about ± 50 mV of V should be well regulated and used only for the A/D converter. The V supply can be between 4.5 and 5.5 volts and must be able to source approximately 5 mA (see the datasheet for actual specifications). V...
Page 286 ANALOG-TO-DIGITAL CONVERTER In many applications, it is less critical to record the absolute accuracy of an input than it is to de- tect that a change has occurred. This approach is acceptable as long as the converter is monotonic and has no missing codes. That is, increasing input voltages produce adjacent, unique output codes that are also increasing.
Page 287 8XC196NT USER’S MANUAL FINAL CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO (Vref – 1.5 (LSB)). ACTUAL CHARACTERISTIC OF AN IDEAL A/D CONVERTER THE VOLTAGE CHANGE BETWEEN THE ADJACENT CODE TRANSITIONS (THE “CODE WIDTH”) IS = 1 LSB.
Page 288 ANALOG-TO-DIGITAL CONVERTER FULL SCALE ERROR IDEAL CHARACTERISTIC ABSOLUTE ERROR ACTUAL CHARACTERISTIC ZERO OFFSET 6 1/2 INPUT VOLTAGE (LSBs) A0084-01 Figure 11-10. Actual and Ideal A/D Conversion Characteristics The actual characteristic of a hypothetical 3-bit converter is not perfect. When the ideal charac- teristic is overlaid with the actual characteristic, the actual converter is seen to exhibit errors in the locations of the first and final code transitions and in code widths, as shown in Figure 11-10.
Page 289 8XC196NT USER’S MANUAL Differential nonlinearity is the degree to which actual code widths differ from the ideal one-LSB width. It provides a measure of how much the input voltage may have changed in order to produce a one-count change in the conversion result. In the 10-bit converter, the code widths are ideally 5 mV (V / 1024).
Page 290 ANALOG-TO-DIGITAL CONVERTER IDEAL FULL-SCALE CODE TRANSITION IDEAL STRAIGHT LINE TRANSFER FUNCTION ACTUAL FULL-SCALE CODE TRANSITION DIFFERENTIAL TERMINAL BASED NON-LINEARITY CHARACTERISTIC (POSITIVE) (corrected for zero-offset and full-scale error) IDEAL CODE WIDTH ACTUAL CHARACTERISTIC NON-LINEARITY DIFFERENTIAL NON-LINEARITY (NEGATIVE) IDEAL CODE WIDTH ACTUAL FIRST TRANSITION IDEAL FIRST TRANSITION 6 1/2 INPUT VOLTAGE (LSBs)
Page 292: Minimum Hardware Considerations
Minimum Hardware Considerations...
Page 294: Minimum Connections
CHAPTER 12 MINIMUM HARDWARE CONSIDERATIONS The 8XC196NT has several basic requirements for operation within a system. This chapter de- scribes options for providing the basic requirements and discusses other hardware considerations. 12.1 MINIMUM CONNECTIONS Table 12-1 lists the signals that are required for the device to function and Figure 12-1 shows the connections for a minimum configuration.
Page 295: Unused Inputs
8XC196NT USER’S MANUAL Table 12-1. Minimum Required Signals(Continued) Signal Type Description Name XTAL1 Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1.
Page 296 MINIMUM HARDWARE CONSIDERATIONS (Note 1) 20 pF 20 pF XTAL2 XTAL1 RESET# (Note 2) 0.01 µF 4.7 µF BUSWIDTH (Note 3) READY 1 µF 1 µF BHE# ANGND Port 5 / Bus Control (Note 4) Input-only INST Port Pins (Note 5) 8XC196 Device Notes: 1.
Page 297: Applying And Removing Power
8XC196NT USER’S MANUAL 12.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth- erwise, operation might be unpredictable.
Page 298: Providing The Clock
MINIMUM HARDWARE CONSIDERATIONS If the A/D converter will be used, connect V to a separate reference supply to minimize noise during A/D conversions. Even if the A/D converter will not be used, V and ANGND must be connected to provide power to port 0. Refer to “Analog Ground and Reference Voltages” on page 11-13 for a detailed discussion of A/D power and ground recommendations.
Page 299 8XC196NT USER’S MANUAL To internal circuitry V CC XTAL2 XTAL1 (Output) (Input) Oscillator Enable# (from powerdown circuitry) V SS A0076-03 Figure 12-3. On-chip Oscillator Circuit Figure 12-4 shows the connections between the external crystal and the device. When designing an external oscillator circuit, consider the effects of parasitic board capacitance, extended oper- ating temperatures, and crystal specifications.
Page 300: Using A Ceramic Resonator Instead Of A Crystal Oscillator
MINIMUM HARDWARE CONSIDERATIONS XTAL1 XTAL1 8XC196 8XC196 Device Device XTAL2 XTAL2 Quartz Crystal Quartz Crystal Note: Note: Mount oscillator components close to the device and use Mount oscillator components close to the device and use short, direct traces to XTAL1, XTAL2, and V ss . When short, direct traces to XTAL1, XTAL2, and V ss .
Page 301: Resetting The Device
8XC196NT USER’S MANUAL V CC V CC 4.7 kΩ † 4.7 kΩ † External External XTAL1 XTAL1 Clock Input Clock Input 8XC196 Device 8XC196 Device Clock Driver Clock Driver No Connection No Connection XTAL2 XTAL2 † Required if TTL driver is used. Not needed if CMOS driver is used.
Page 302 MINIMUM HARDWARE CONSIDERATIONS Figure 12-7 shows the reset-sequence timing. Depending upon when RESET# is brought high, the CLKOUT signal may become out of phase with the PH1 internal clock. When this occurs, the clock generator immediately resynchronizes CLKOUT as shown in Case 2. Internal Reset RESET#...
Page 303: Generating An External Reset
8XC196NT USER’S MANUAL Internal External V CC Clock Reset State Machine Internal † R RST Reset Trigger Signal Count Complete RESET# ~200 Ω RST Instruction WDT Overflow IDLPD Invalid Key USFR.0 (F OSC < 100 kHz) † See the datasheet for minimum and maximum R values.
Page 304 MINIMUM HARDWARE CONSIDERATIONS RESET# RESET# 4.7 µF 4.7 µF 8XC196 Device 8XC196 Device A0276-01 A0276-01 Figure 12-9. Minimum Reset Circuit Other devices in the system may not be reset because the capacitor will keep the voltage above . Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer the system-reset pulse.
Page 305: Issuing The Reset (Rst) Instruction
8XC196NT USER’S MANUAL 12.5.2 Issuing the Reset (RST) Instruction The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times. It also clears the processor status word (PSW), sets the master program counter (PC) to FF2080H, and resets the special function registers (SFRs).
Page 306: Special Operating Modes
Special Operating Modes...
Page 308: Special Operating Mode Signals And Registers
CHAPTER 13 SPECIAL OPERATING MODES The 8XC196NT has two power saving modes: idle and powerdown. It also provides an on-circuit emulation (ONCE) mode that electrically isolates the device from the other system components. This chapter describes each mode and explains how to enter and exit each. (Refer to Appendix A for descriptions of the instructions discussed in this chapter, to Appendix B for descriptions of signal status during each mode, and to Appendix C for details about the registers.)
Page 309 8XC196NT USER’S MANUAL Table 13-1. Operating Mode Control Signals (Continued) Signal Port Pin Type Description Name P5.4 Test- Test-mode entry mode If this pin is held low during reset, the device will enter a reserved test entry mode, so exercise caution if you use this pin for input. If you choose...
Page 310: Reducing Power Consumption
SPECIAL OPERATING MODES 13.2 REDUCING POWER CONSUMPTION Both power-saving modes conserve power by disabling portions of the internal clock circuitry (Figure 13-1). The following paragraphs describe both modes in detail. Disable Clock Input (Powerdown) Divide-by-two XTAL1 Circuit Disable Clocks (Powerdown) XTAL2 Peripheral Clocks (PH1, PH2) Clock...
Page 311: Powerdown Mode
8XC196NT USER’S MANUAL The device enters idle mode after executing the IDLPD #1 instruction. Either an interrupt or a hardware reset will cause the device to exit idle mode. Any enabled interrupt source, either inter- nal or external, can cause the device to exit idle mode. When an interrupt occurs, the CPU clocks restart and the CPU executes the corresponding interrupt service or PTS routine.
Page 312: Entering Powerdown Mode
SPECIAL OPERATING MODES 13.4.2 Entering Powerdown Mode Before entering powerdown, complete the following tasks: • Complete all serial port transmissions or receptions. Otherwise, when the device exits powerdown, the serial port activity will continue where it left off and incorrect data may be transmitted or received.
Page 313: Generating A Hardware Reset
8XC196NT USER’S MANUAL 13.4.3.2 Generating a Hardware Reset The device will exit powerdown if RESET# is asserted. If the design uses an external clock input signal rather than the on-chip oscillator, RESET# must remain low for at least 16 state times. If the design uses the on-chip oscillator, then RESET# must be held low until the oscillator has sta- bilized.
Page 314 SPECIAL OPERATING MODES When using an external interrupt signal to exit powerdown mode, we recommend that you con- nect the external RC circuit shown in Figure 13-3 to the V pin. The discharging of the capacitor causes a delay that allows the oscillator to stabilize before the internal CPU and peripheral clocks are enabled.
Page 315 8XC196NT USER’S MANUAL EXTINT 200 µA C 1 Discharge R 1 x C 1 Recovery V PP , Volts Time Constant Pullup On Code Execution Resumes Time, ms A0151-01 Figure 13-4. Typical Voltage on the V Pin While Exiting Powerdown Select a resistor that will not interfere with the discharge current.
Page 316: Once Mode
Normal operations resume when RESET# goes high. 13.6 RESERVED TEST MODES A special test-mode-entry pin (P5.4) is provided for Intel’s in-house testing only. These test modes can be entered accidentally if you configure the test-mode-entry pin as an input and hold it low during the rising edge of RESET#.
Page 318: Interfacing With External Memory
Interfacing with External Memory...
Page 320: Internal And External Addresses
CHAPTER 14 INTERFACING WITH EXTERNAL MEMORY The device can interface with a variety of external memory devices. It supports either a fixed 8- bit bus width, a fixed 16-bit bus width, or a dynamic 8-bit/16-bit bus width; internal control of wait states for slow external memory devices;...
Page 321: External Memory Interface Signals
8XC196NT USER’S MANUAL 14.2 EXTERNAL MEMORY INTERFACE SIGNALS Table 14-2 describes the external memory interface signals. For some signals, the pin has an al- ternate function (shown in the Multiplexed With column). In some cases the alternate function is a port signal (e.g., P2.7). Chapter 6, “I/O Ports,” describes how to configure a pin for its I/O port function and for its special function.
Page 322 INTERFACING WITH EXTERNAL MEMORY Table 14-2. External Memory Interface Signals (Continued) Function Multiplexed Type Description Name With BHE# Byte High Enable P5.5/WRH# The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#.
Page 323 HOLD# and HLDA# and whether the device is executing from internal or external program memory. If the 8XC196NT receives an interrupt request while it is in hold and it is executing code from internal memory, it asserts INTOUT# immedi- ately.
Page 324: Chip Configuration Registers And Chip Configuration Bytes
INTERFACING WITH EXTERNAL MEMORY Table 14-2. External Memory Interface Signals (Continued) Function Multiplexed Type Description Name With READY Ready Input P5.6 This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally.
Page 325 8XC196NT USER’S MANUAL Address: FF2018H CCR0 Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 326 INTERFACING WITH EXTERNAL MEMORY Address: FF2018H CCR0 (Continued) Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 327 8XC196NT USER’S MANUAL Address: FF201AH CCR1 Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit controls whether CCR2 is loaded.
Page 328 INTERFACING WITH EXTERNAL MEMORY Address: FF201AH CCR1 (Continued) Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit controls whether CCR2 is loaded.
Page 329: Bus Width And Multiplexing
8XC196NT USER’S MANUAL Address: FF201CH CCR2 Reset State: The chip configuration register 2 (CCR2) supports extended addressing. It selects either 64-Kbyte or 1-Mbyte addressing mode and controls whether the internal OTPROM is mapped into both page 0FFH and page 00H or into page FFH only. This register is loaded from CCB2 if the LDCCB2 bit (bit 0) of CCR1 is set;...
Page 330 INTERFACING WITH EXTERNAL MEMORY Bus Control Bus Control 4-bit Extended Address A19:16 4-bit Extended Address A19:16 (EPORT) (EPORT) 8-bit Address High 16-bit Multiplexed AD15:8 Address/Data (Port 4) AD15:0 8-bit Multiplexed (Ports 4 and 3) Address/Data AD7:0 (Port 3) 8XC196 8XC196 Device Device 16-bit Bus...
Page 331: Timing Requirements For Buswidth
8XC196NT USER’S MANUAL XTAL1 CLKOUT (MIN) LLGV CLGX BUSWIDTH Valid AVGV Data Address A0164-02 Figure 14-5. BUSWIDTH Timing Diagram The BUSWIDTH signal can be used in numerous applications. For example, a system could store code in a 16-bit memory device and data in an 8-bit memory device. The BUSWIDTH signal could be tied to the chip-select input of the 8-bit memory device (shown in Figure 14-13 on page 14-26).
Page 332: 16-Bit Bus Timings
INTERFACING WITH EXTERNAL MEMORY 14.4.2 16-bit Bus Timings When the device is configured to operate in the 16-bit bus-width mode, lines AD15:0 form a 16- bit multiplexed address/data bus. Figure 14-6 shows an idealized timing diagram for the external read and write cycles. (Comprehensive timing specifications are shown in Figure 14-25). The rising edge of the address latch enable (ALE) indicates that the device is driving an address onto the bus (A19:16 and AD15:0).
Page 333 8XC196NT USER’S MANUAL XTAL1 CLKOUT Valid BUSWIDTH A19:16 Extended Address Out Address Out Data In AD15:0 (Read) INST Valid Extended Address Out A19:16 Address Out Data Out AD15:0 (Write) A0281-02 Figure 14-6. Timings for 16-bit Buses 14-14...
Page 334: 8-Bit Bus Timings
INTERFACING WITH EXTERNAL MEMORY 14.4.3 8-bit Bus Timings When the device is configured to operate in the 8-bit bus mode, lines AD7:0 form a multiplexed lower address and data bus. Lines AD15:8 are not multiplexed; the upper address is latched and remains valid throughout the bus cycle.
Page 335 8XC196NT USER’S MANUAL XTAL1 CLKOUT BUSWIDTH A19:16 Extended Address Out Extended Address Out Address Out Address Out AD15:8 Address Address Low data in High data in AD7:0 +1 Out (Read) INST A19:16 Extended Address Out Extended Address Out Address Address...
Page 336: Wait States (Ready Control)
An external device can use the READY input to request wait states in addition to the wait states that are generated internally by the 8XC196NT device. When an address is placed on the bus for an external bus cycle, the external device can pull the READY signal low to indicate it is not ready.
Page 337 8XC196NT USER’S MANUAL Setup and hold timings must be met when using the READY signal to insert wait states into a bus cycle (see Table 14-3 and Figure 14-8). Because a decoded, valid address is used to generate the READY signal, the setup time is specified relative to the address being valid. This specification,...
Page 338: Bus-Hold Protocol
INTERFACING WITH EXTERNAL MEMORY CLKOUT CLYX (MIN) CLYX (MAX) READY AVYV Extended Address Out A19:16 Address Out Data AD15:0 AD15:0 Address Address Out Data Out A0283-02 Figure 14-8. READY Timing Diagram 14.6 BUS-HOLD PROTOCOL The device supports a bus-hold protocol that allows external devices to gain control of the ad- dress/data bus.
Page 339 8XC196NT USER’S MANUAL CLKOUT HVCH HVCH Hold Latency HOLD# CLHAL CLHAH HLDA# CLBRL CLBRH BREQ# HALAZ HAHAX HALBZ HAHBV BHE#, INST Weakly Driven Inactive RD#, WR# WRL#, WRH# CLLH Weakly Driven Inactive ADV# ADV# weakly driven Start of strongly driven ADV# and ALE A0165-02 Figure 14-9.
Page 340: Enabling The Bus-Hold Protocol
In response, the 8XC196NT drives HLDA# high and assumes control of the bus. If the 8XC196NT has a pending external bus cycle while it is in hold, it asserts BREQ# to request control of the bus. After the external device responds by driving HOLD# high, the 8XC196NT exits hold and then deasserts BREQ# and HLDA#.
Page 341: Disabling The Bus-Hold Protocol
8XC196NT USER’S MANUAL 14.6.2 Disabling the Bus-hold Protocol To disable hold requests, clear WSR.7. The device does not take control of the bus immediately after HLDEN is cleared. Instead, it waits for the current HOLD# request to finish and then dis- ables the bus-hold feature and ignores any new requests until the bit is set again.
Page 342: Bus-Control Modes
INTERFACING WITH EXTERNAL MEMORY If the device is reset while in hold, bus contention can occur. For example, a CPU-only device (80C196NT) would try to fetch the chip configuration byte from external memory after RESET# was brought high. Bus contention would occur because both the external device and the micro controller would attempt to access memory.
Page 343 8XC196NT USER’S MANUAL WR# or RD# WR# or RD# BHE# AD7:0 Valid Addr Low Data Out AD15:0 AD15:8 Address High Addr Data Out A19:16 Extended Address A19:16 Extended Address 16-bit Bus Cycle 8-bit Bus Cycle A0284-02 Figure 14-10. Standard Bus Control When the device is configured to use a 16-bit bus, separate low- and high-byte write signals must be generated for single-byte writes.
Page 344 INTERFACING WITH EXTERNAL MEMORY Figure 14-12 shows an 8-bit system with both flash and RAM. The flash is the lower half of mem- ory, and the RAM is the upper half. This system configuration uses the most-significant address bit (A19) as the chip-select signal and ALE as the address-latch signal. The lower address lines, AD7:0, are latched because these lines are carry both address and data information.
Page 345 8XC196NT USER’S MANUAL Figure 14-13 shows a system that uses the dynamic bus-width feature. (The CCR bits, BW0 and BW1, are set.) Code is executed from the two flash memories and data is stored in the byte-wide RAM. The RAM is in low memory. It is selected by driving A19 low, which also selects the 8- bit bus-width mode by driving the BUSWIDTH signal low.
Page 346: Write Strobe Mode
INTERFACING WITH EXTERNAL MEMORY 14.7.2 Write Strobe Mode The write strobe mode eliminates the need to externally decode high- and low-byte writes to an external 16-bit RAM or Flash device in 16-bit bus mode. When the write strobe mode is selected, the device generates WRL# and WRH# instead of WR# and BHE#.
Page 347 8XC196NT USER’S MANUAL Figure 14-15 shows a 16-bit system with two Flash memories and two RAMs. It is configured to use the write strobe mode. ALE latches the address; A19 is the chip-select signal for the memory devices. WRL# is asserted during low byte writes and word writes. WRH# is asserted during high byte writes and word writes.
Page 348: Address Valid Strobe Mode
INTERFACING WITH EXTERNAL MEMORY 14.7.3 Address Valid Strobe Mode When the address valid strobe mode is selected, the device generates the address valid signal (ADV#) instead of the address latch enable signal (ALE). ADV# is asserted after an external ad- dress is valid (see Figure 14-16).
Page 349 8XC196NT USER’S MANUAL A19:16 Extended Address AD15:0 Address Data ADV# RD#/WR# Bus Idle Next Bus Cycle A0290-02 Figure 14-17. Comparison of ALE and ADV# Bus Cycles 14-30...
Page 350 INTERFACING WITH EXTERNAL MEMORY Figure 14-18 and Figure 14-19 show sample circuits that use address valid strobe mode. Figure 14-18 shows a simple 8-bit system with a single flash. It is configured for the address valid strobe mode. This system configuration uses the ADV# signal as both the flash chip-select signal and the address-latch signal.
Page 351 8XC196NT USER’S MANUAL Figure 14-19 shows a 16-bit system with two flash memories. This system configuration uses the ADV# signal as both the flash chip-select signal and the address-latch signal. BUSWIDTH A17:16 A16:15 A16:15 A15:8 A15:8 74AC AD15:8 A14:7 A14:7...
Page 352: Address Valid With Write Strobe Mode
INTERFACING WITH EXTERNAL MEMORY 14.7.4 Address Valid with Write Strobe Mode When the address valid with write strobe mode is selected, the device generates the ADV#, WRL#, and WRH# bus-control signals. This mode is used for a simple system using external 16- bit RAM.
Page 353: Bus Timing Modes
8XC196NT USER’S MANUAL V CC BUSWIDTH A17:16 A16:15 A16:15 A15:8 74AC AD15:8 A14:7 A14:7 D15:8 ADV# D7:0 128K×8 128K×8 8XC196 (High) (Low) A7:1 74AC AD7:0 A6:0 A6:0 WRH# WRL# A0294-02 Figure 14-21. 16-bit System with RAM 14.8 BUS TIMING MODES The device has selectable bus timing modes controlled by the MSEL0 and MSEL1 bits (bits 6 and 7) of CCR1.
Page 354 INTERFACING WITH EXTERNAL MEMORY MODE 3 CLKOUT = 1 T = 1 T T RHDZ RLDV DATA ADDR DATA ADDR DATA ADDR = 3 T AVDV MODE 0 = 3 T RLDV = 1 T RHDZ DATA ADDR DATA ADDR DATA = 5 T AVDV...
Page 355: Mode 3, Standard Mode
8XC196NT USER’S MANUAL Table 14-7. Modes 0, 1, 2, and 3 Timing Comparisons Timing Specifications (in T ) Note 1 Mode CLLH CHLH AVLL AVDV RLRH RHDZ RLDV Mode 3 Mode 0 Mode 1 Mode 2 NOTES: These are ideal timing values for purposes of comparison only. They do not include internal device delays.
Page 356: Mode 2, Long Read/Write With Early Address
INTERFACING WITH EXTERNAL MEMORY XTAL 1 XHCH CHCL CLCL CLKOUT CLLL CHLH LHLH ALE/ADV# LHLL LLRL RHLH RLRH RLDV RLAZ AVLL LLAX RHDZ Bus Read Address Data In D15:0 AD15:0 8- and16-bit AVDV Bus Mode LLWL WLWH QVWH WHQX Bus Write Address Out Data Out AD15:0...
Page 357 8XC196NT USER’S MANUAL XTAL 1 XHCH CHCL CLCL CLKOUT CLLL CHLH LHLH ALE/ADV# LHLL LLRL RHLH RLRH RLDV RLAZ RHDZ AVLL LLAX Bus Read Address Data In D15:0 AD15:0 8- and 16-bit AVDV Bus Mode LLWL WLWH QVWH WHQX Bus Write...
Page 358: Design Considerations
INTERFACING WITH EXTERNAL MEMORY 14.8.5 Design Considerations In all bus timing modes, for 16-bit bus-width operation, latch the upper and lower address/data lines. In modes 1 and 2, for 8-bit bus-width operation, also latch the upper and lower address/data lines; the upper address lines are not driven throughout the entire bus cycle (see Figures 14-23 and 14-24).
Page 359 Definition The External Memory System Must Meet These Specifications Address Valid to Input Data Valid AVDV Maximum time the memory device has to output valid data after the 8XC196NT outputs a valid address. RD# High to Input Data Float RHDZ Time after RD# is inactive until the memory system must float the bus.
Page 360 Time between RD# going inactive and the next ALE/ADV#. Useful in calculating time between inactive and next address valid. RD# Low to Address Float RLAZ Used to calculate when the 8XC196NT stops driving address on the bus. RD# Low to RD# High RLRH RD# pulse width.
Page 361 8XC196NT USER’S MANUAL Table 14-9. AC Timing Definitions (Continued) Symbol Definition The 8XC196NT Meets These Specifications (Continued) WR# High to ALE/ADV# High WHLH Time between WR# going inactive and next ALE/ADV#. Also used to calculate WR# inactive and next address valid.
Page 362: Programming The Nonvolatile Memory
Programming the Nonvolatile Memory...
Page 364: Programming Methods
CHAPTER 15 PROGRAMMING THE NONVOLATILE MEMORY The 87C196NT contains 32 Kbytes of one-time-programmable read-only memory (OTPROM). OTPROM is similar to EPROM, but it comes in an unwindowed package and cannot be erased. You can either program the OTPROM yourself or have the factory program it as a quick-turn ROM product (this option may not be available for all devices).
Page 365: Otprom Memory Map
Reserved (each location must contain FFH) FF205E FF205D PTS vectors FF2040 † Intel manufacturing uses this location to determine whether to program the OFD bit. Customers with QROM or MROM codes who desire oscillator failure detection should equate this location to the value 0CDEH. 15-2...
Page 366: Security Features
Lower interrupt vectors FF2000 † Intel manufacturing uses this location to determine whether to program the OFD bit. Customers with QROM or MROM codes who desire oscillator failure detection should equate this location to the value 0CDEH. 15.3 SECURITY FEATURES Several security features enable you to control access to both internal and external memory.
Page 367: Controlling Access To The Otprom During Normal Operation
8XC196NT USER’S MANUAL 15.3.1.1 Controlling Access to the OTPROM During Normal Operation During normal operation, the lock bits in CCB0 control read and write accesses to the OTPROM. Table 15-2 describes the options. You can program the CCBs using any of the programming methods.
Page 368 PROGRAMMING THE NONVOLATILE MEMORY These protection levels are provided by the PCCB0 lock bits, the CCB0 lock bits, and the internal security key (Table 15-3). When entering programming modes, the reset sequence loads the PCCBs into the chip configuration registers. It also loads CCB0 into internal RAM to provide an additional level of security.
Page 369: Controlling Fetches From External Memory
8XC196NT USER’S MANUAL You can program the internal security key in either auto or slave programming mode. Once the security key is programmed, you must provide a matching key to gain access to any programming mode. For auto programming and ROM-dump modes, a matching security key must reside in ex- ternal memory.
Page 370: Enabling The Oscillator Failure Detection Circuitry
You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this reason, Intel cannot test the bits before shipment. However, Intel does test the features that the UPROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells them- selves.
Page 371: Programming Pulse Width
† 0778H † Intel manufacturing uses location FF2016H to determine whether to program the OFD bit. Customers with QROM or MROM codes who desire the OFD feature should equate location FF2016H to the value 0CDEH. 15.4 PROGRAMMING PULSE WIDTH The programming pulse width is controlled in different ways depending on the programming mode.
Page 372: Modified Quick-Pulse Algorithm
A verification error deasserts the PVER signal, but does not stop the programming routine. This process repeats until each OTPROM word has been programmed and verified. Intel guarantees lifetime data retention for a device pro- grammed with the modified quick-pulse algorithm.
Page 373 8XC196NT USER’S MANUAL From Auto or Slave Programming Start PPW Timer Write Data to OTPROM Enable Interrupts Enter Idle Mode Wait for PPW Timer Interrupt Required Writes Done Compare Programmed Locations and Set Flags Return A0190-03 Figure 15-3. Modified Quick-pulse Algorithm Auto programming repeats the pulse five times, using the pulse width you specify in the external EPROM.
Page 374: Programming Mode Pins
PROGRAMMING THE NONVOLATILE MEMORY 15.6 PROGRAMMING MODE PINS Figure 15-4 illustrates the signals used in programming and Table 15-5 describes them. The EA#, , and PMODE pins combine to control entry into programming modes. You must configure the PMODE (P0.7:4) pins to select the desired programming mode (see Table 15-6 on page 15-13).
Page 375 8XC196NT USER’S MANUAL Table 15-5. Pin Descriptions (Continued) Special Program- Port Pin Function Type ming Description Signal Mode P2.1 PALE# Slave Programming ALE Input During slave programming, a falling edge causes the device to read a command and address from the PBUS.
Page 376: Entering Programming Modes
PROGRAMMING THE NONVOLATILE MEMORY Table 15-5. Pin Descriptions (Continued) Special Program- Port Pin Function Type ming Description Signal Mode P1.2:1, PBUS Auto Address/Command/Data Bus P4.7:5, ROM- During auto programming and ROM-dump, ports 3 and 4 P3.7:0 dump serve as a regular system bus to access external memory.
Page 377: Power-Up And Power-Down Sequences
8XC196NT USER’S MANUAL 15.7.2 Power-up and Power-down Sequences When you are ready to begin programming, follow these power-up and power-down procedures. WARNING Failure to observe these warnings will cause permanent device damage. • Voltage must not be applied to V while V is low.
Page 378: Slave Programming Mode
PROGRAMMING THE NONVOLATILE MEMORY 15.8 SLAVE PROGRAMMING MODE Slave programming mode allows you to program and verify the entire OTPROM array, including the PCCBs and UPROM bits, by using an EPROM programmer. In this mode, ports 3 and 4 serve as the PBUS, transferring commands, addresses, and data. The least-significant bit of the PBUS (P3.0) controls the command (1 = program word;...
Page 379: Slave Programming Circuit And Memory Map
8XC196NT USER’S MANUAL Table 15-7. Device Signature Word and Programming Voltages Signature Word Programming V Programming V Device Location Value Location Value Location Value 8XC196NT 0070H 87AFH 0072H 0073H 0A0H 15.8.2 Slave Programming Circuit and Memory Map Figure 15-5 shows the circuit diagram and Table 15-8 shows the memory map for slave program- ming mode.
Page 380: Operating Environment
PROGRAMMING THE NONVOLATILE MEMORY Table 15-8. Slave Programming Mode Memory Map Description Address Comments OTPROM 2000–9FFFH OTPROM Cells 0778H OTPROM Cell † 0758H UPROM Cell † 0718H UPROM Cell PCCB 0218H Test EPROM Programming voltages (see Table 15-7 on page 15-16) 0072H, 0073H Read Only Signature word 0070H Read Only...
Page 381 8XC196NT USER’S MANUAL Address: FF201CH, FF201AH, FF2018H CCR2, CCR1, CCR0 Reset State: from CCBs XXH, XXH, XXH Reset State: see bit descriptions The chip configuration registers (CCRs) control OTPROM mapping, addressing mode, bus configu- ration, wait states, powerdown mode, and internal memory protection. These registers are loaded from the PCCBs during programming modes and from the CCBs for normal operation.
Page 382: Slave Programming Routines
PROGRAMMING THE NONVOLATILE MEMORY 15.8.4 Slave Programming Routines The slave programming mode algorithm consists of three routines: the address/command decod- ing routine, the program word routine, and the dump word routine. The address/command decoding routine (Figure 15-7) reads the PBUS and transfers control to the program word or dump word routine based on the value of P3.0.
Page 383 8XC196NT USER’S MANUAL Other PMODE = 05H Modes PALE# (P2.1) = 0 Read Data From PBUS PVER Deassert CPVER (P2.0) = 1 Assert PVER PALE# (P2.1)= 0 Check Address Dump Word P3.0 = 1 Routine Program Word Routine A0193-02 Figure 15-7. Address/Command Decoding Routine...
Page 384 PROGRAMMING THE NONVOLATILE MEMORY From Address/ Command Decoder PROG# (P2.2)=0 Lock Bits Verify Read Data Security Key Enabled from PBUS Execute Modified Keys Loop Quick-Pulse Algorithm Match Forever then Return Deassert Programming PVER (P2.0 = 0) Verifies Read Data from PBUS Assert PVER (P2.0 = 1) PROG#...
Page 385 8XC196NT USER’S MANUAL Figure 15-9 shows the timings of the program word command with a repeated programming pulse and auto increment. Asserting PALE# latches the command and address on the PBUS. Asserting PROG# latches the data on the PBUS and starts the programming sequence. The PROG# signal controls the programming pulse width.
Page 386 PROGRAMMING THE NONVOLATILE MEMORY From Address/ Command Decoder Lock Bits Enabled Get Data from OPTROM PROG# (P2.2) = 0 Write Data to PBUS PROG# (P2.2) = 1 Write 0FFFFH to PBUS PALE# To Address/ (P2.1) = 0 Command Decoder AINC# (P2.4) = 0 Increment Address by 2...
Page 387: Timing Mnemonics
8XC196NT USER’S MANUAL Figure 15-11 shows the timings of the dump word command. PROG# governs when the device drives the bus. The timings before the dump word command are the same as those shown in Fig- ure 15-9. In the dump word mode, the AINC# pin can remain active and toggling. The PROG# pin automatically increments the address.
Page 388: Auto Programming Mode
PROGRAMMING THE NONVOLATILE MEMORY Table 15-9. Timing Mnemonics (Continued) Mnemonic Description PROG# High to Next PROG# Low. PHPL PROG# High to AINC# Low. PHIL AINC# Pulse Width. ILIH PVER Hold After AINC# Low. ILVH AINC# Low to PROG# Low. ILPL PROG# High to PVER Valid.
Page 389 8XC196NT USER’S MANUAL 20 pF 20 pF 100 kΩ XTAL1 XTAL2 Reset RESET# +5.0V 1 kΩ 74HC14 1.0µF READY/P5.6 10µF BUSWIDTH/P5.7 +12.50V RD#/P5.3 P0.7/ PMODE.3 P0.6/ P1.2 PMODE.2 P1.1 P0.5/ PMODE.1 AD13:8 A13:8 P0.4/ PMODE.0 ANGND LE OE# 270kΩ ALE/P5.0 27(C)512 P2.7/PACT#...
Page 390: Operating Environment
PROGRAMMING THE NONVOLATILE MEMORY Table 15-10. Auto Programming Memory Map Address Address Output from Internal Using Circuit 8XC196 OTPROM in Figure Description Device Address 15-12 (A15:0) (P1.2:1, A13:0) 4014H 14H Programming pulse width (PPW) LSB. 4015H 15H Programming pulse width (PPW) MSB. 4020–402FH FF2020–FF202FH 0020–002FH Security key for verification.
Page 391 8XC196NT USER’S MANUAL Other PMODE = 0CH Modes Lock Bits Enabled Verify Security Key Loop Pass Forever Assert PACT# Load PPW Get External Data Data = 0FFFFH Execute Modified Quick-Pulse Algorithm then Return Error Programming Clear PVER Increment Address Pointer...
Page 392: Auto Programming Procedure
PROGRAMMING THE NONVOLATILE MEMORY If the security key verification is successful, the routine loads the programming pulse width (PPW) value from the external EPROM into the internal PPW register. It then asserts PACT#, in- dicating that programming has begun. (PACT# is also active during reset, although no program- ming is in progress.) PVER is initially asserted and remains asserted unless an error is detected, in which case it is deasserted.
Page 393: Rom-Dump Mode
8XC196NT USER’S MANUAL Using another blank EPROM device, follow these steps to program only CCB0. — Place the programming pulse width (PPW) in external locations 14H–15H. — Place the appropriate CCB0 value in external location 4018H. — Place the security key to be verified in external EPROM locations 0020H–002FH. This value must match the security key programmed in step 1.
Page 394: Serial Port Programming Mode
Special software, called IBSP196, simplifies communication between the device and a smart ter- minal. This software is available free of charge through the Intel BBS. (See “Bulletin Board Sys- tem (BBS)” on page 1-9.) NOTE Serial port programming mode has no provision for security-key verification.
Page 395 8XC196NT USER’S MANUAL 30 pF 30 pF XTAL1 XTAL2 RESET# 10 µF P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND READY/P5.6 BUSWIDTH/5.7 P2.1/RXD P2.0/TXD 0.01 µF 87C196 Device 2N2222A 1.8kΩ 1N914 1.8kΩ 2N2907 1.8kΩ 1.8kΩ 1.8kΩ 1N914 10µF A0298-04 Figure 15-14. Serial Port Programming Mode Circuit...
Page 396: Changing Serial Port Programming Defaults
PROGRAMMING THE NONVOLATILE MEMORY Because the RISM begins at location 2000H in serial port programming mode, the OTPROM lo- cations are automatically remapped as shown in Table 15-11. For example, to access OTPROM location FF2000H in serial port programming mode, you must address it as A000H. Table 15-11.
Page 397: Executing Programs From Internal Ram
8XC196NT USER’S MANUAL 15.10.3 Executing Programs from Internal RAM For those wanting to execute user programs from internal RAM while in serial port programming mode, the RISM allows you to initialize the user program counter (PC), window selection register (WSR), and processor status word (PSW). Table 15-13 lists the registers, the default assumed by the RISM, and the test ROM address to which you may write new values.
Page 398: Rism Command Descriptions
PROGRAMMING THE NONVOLATILE MEMORY When a receive interrupt occurs, the RISM checks the data value and the DLE flag. If the data value is greater than 1FH or if the DLE flag is set, the received byte is considered data and is stored in the DATA register (58H).
Page 399 8XC196NT USER’S MANUAL Table 15-14. RISM Command Descriptions (Continued) Value Command Description READ_WORD Puts the contents of the (word) memory address pointed to by the ADDR register into the low word of the DATA register. Memory Addr. ADDR DATA 2215...
Page 400: Rism Command Examples
PROGRAMMING THE NONVOLATILE MEMORY Table 15-14. RISM Command Descriptions (Continued) Value Command Description INDIRECT Puts the word from the memory address pointed to by the ADDR register into the ADDR register. Memory Addr. ADDR 2217 2216 Before command After command PUSHes the user PC, PSW, and WSR onto the stack and starts your program from the location contained in the user PC.
Page 401: Example 2 - Reading Otprom Contents
8XC196NT USER’S MANUAL Because an OTPROM location is being altered, V must be at +12.5 volts. RISM commands must be sent across the serial port one byte at a time, and a SET_DLE_FLAG command must precede any data byte that is less than 1FH. The address being modified must first be loaded into the DATA register, then transferred to the ADDR register.
Page 402: Example 3 - Loading A Program Into Internal Code Ram
PROGRAMMING THE NONVOLATILE MEMORY Send Comments (Example 2) DATA ADDR Data. High byte of address to DATA register. Data. Low byte of address to DATA register. DATA_TO_ADDR. Move address to DATA register. READ_WORD. Put word at A080H into DATA. TRANSMIT. Transmit low byte of DATA across the serial port, increment ADDR by one, and shift DATA right long by eight bits.
Page 403 8XC196NT USER’S MANUAL Send Comments (Example 3) DATA ADDR SET_DLE_FLAG. Next data byte is < 1FH. Data. High byte of address 0400H. SET_DLE_FLAG. Next data byte is < 1FH. Data. Low byte of address 0400H. DATA_TO_ADDR. Move address to ADDR.
Page 404: Example 4 - Setting The Pc And Executing The Program
PROGRAMMING THE NONVOLATILE MEMORY Send Comments (Example 3) DATA ADDR Data. High byte of hex file for location 0405H. Data. Low byte of hex file for location 0404H. WRITE_WORD. Low word of DATA to memory location 0404 (contents of ADDR). Increment ADDR by two.
Page 405: Writing To Otprom With Examples 3 And 4
8XC196NT USER’S MANUAL Send Comments (Example 4) DATA ADDR WRITE_WORD. Low word of DATA to PC location 005EH (contents of ADDR). Increment ADDR by two. Memory Addresses 005F 005E GO. PUSHes the user PC onto the stack and begins program execution at 0400H. (Had they been changed, GO would also PUSH the PSW and WSR.)
Page 406: Run-Time Programming
PROGRAMMING THE NONVOLATILE MEMORY 15.11 RUN-TIME PROGRAMMING You can program an OTPROM location during normal code execution. To make the OTPROM array accessible, apply V voltage to EA# while you reset the device. Apply V voltage to the pin during the entire programming process. Then simply write to the location to be pro- grammed.
Page 407 8XC196NT USER’S MANUAL The calling routine must pass two parameters to this routine — the data to be programmed (in DATA_TEMP) and the address (in ADDR_TEMP). PROGRAM: PUSHA ;clear PSW, WSR, INT_MASK, INT_MASK1 WSR,#7BH ;select 32-byte window with EPA0_CON COUNT,#5 ;set up for 5 programming cycles...
Page 408 Instruction Set Reference...
Page 410 APPENDIX A INSTRUCTION SET REFERENCE ® This appendix provides reference information for the instruction set of the family of MCS microcontrollers. It defines the processor status word (PSW) flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes, instruction lengths, and execution times.
Page 411 8XC196NT USER’S MANUAL Table A-1. Opcode Map (Left Half) Opcode SKIP CLRB NOTB NEGB XCHB DECB EXTB INCB SJMP bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 AND 3op ADD 3op ANDB 3op...
Page 412 INSTRUCTION SET REFERENCE Table A-1. Opcode Map (Right Half) Opcode SHRA SHRL SHLL SHRAL NORML SHRB SHLB SHRAB XCHB ESTB ESTB SCALL bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SUB 3op MULU 3op (Note 2) SUBB 3op MULUB 3op (Note 2)
Page 413 8XC196NT USER’S MANUAL Table A-2. Processor Status Word (PSW) Flags Mnemonic Description The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand. If a subtraction operation generates a borrow, the carry flag is cleared.
Page 414 INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified register bit on conditional jump in- structions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction on the PSW flags. Table A-3.
Page 415 8XC196NT USER’S MANUAL Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands. Table A-5. Operand Variables Variable Description A 2-bit field within an opcode that selects the basic addressing mode used. This field is present only in those opcodes that allow addressing mode options.
Page 416 INSTRUCTION SET REFERENCE Table A-6. Instruction Set Mnemonic Operation Instruction Format ADD WORDS. Adds the source and DEST, SRC (2 operands) destination word operands and stores the wreg, waop sum into the destination operand. (011001aa) (waop) (wreg) ← (DEST) (DEST) + (SRC) PSW Flag Settings ↑...
Page 417 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ADDCB ADD BYTES WITH CARRY. Adds the source DEST, SRC and destination byte operands and the carry ADDCB breg, baop flag (0 or 1) and stores the sum into the (101101aa) (baop) (breg) destination operand.
Page 418 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ANDB LOGICAL AND BYTES. ANDs the two source DEST, SRC1, SRC2 (3 operands) byte operands and stores the result into the ANDB Dbreg, Sbreg, baop destination operand. The result has ones in (010100aa) (baop) (Sbreg) (Dbreg) only the bit positions in which both operands had a “1”...
Page 419 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format BMOVI INTERRUPTIBLE BLOCK MOVE. Moves a PTRS, CNTREG block of word data from one location in BMOVI lreg, wreg memory to another. The instruction is (11001101) (wreg) (lreg) identical to BMOV, except that BMOVI is interruptible.
Page 420 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format CLEAR WORD. Clears the value of the DEST operand. wreg ← (DEST) (00000001) (wreg) PSW Flag Settings — — CLRB CLEAR BYTE. Clears the value of the DEST operand.
Page 421 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format CMPB COMPARE BYTES. Subtracts the source DEST, SRC byte operand from the destination byte CMPB breg, baop operand. The flags are altered, but the (100110aa) (baop) (breg) operands remain unaffected. If a borrow occurs, the carry flag is cleared;...
Page 422 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DISABLE INTERRUPTS. Disables interrupts. Interrupt-calls cannot occur after this instruction. (11111010) ← Interrupt Enable (PSW.1) PSW Flag Settings — — — — — — DIVIDE INTEGERS. Divides the contents of DEST, SRC the destination long-integer operand by the lreg, waop...
Page 423 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DIVU DIVIDE WORDS, UNSIGNED. Divides the DEST, SRC contents of the destination double-word DIVU lreg, waop operand by the contents of the source word (100011aa) (waop) (lreg) operand, using unsigned arithmetic. It stores the quotient into the low-order word (i.e., the...
Page 424 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DJNZW DECREMENT AND JUMP IF NOT ZERO WORD. Decrements the value of the word DJNZW wreg,cadd operand by 1. If the result is 0, control passes (11100001) (wreg) (disp) to the next sequential instruction.
Page 425 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EBMOVI EXTENDED INTERRUPTABLE BLOCK PTRS, CNTREG MOVE. Moves a block of word data from one EBMOVI prt2_reg, wreg memory location to another. This instruction (11100100) (wreg) (p2_reg) allows you to move blocks of up to 64K words between any two locations in the 16-Mbyte address space.
Page 426 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ECALL EXTENDED CALL. Pushes the contents of the program counter (the return address) ECALL cadd onto the stack, then adds to the program (1111 0001) (disp-low) (disp-high) (disp-ext) counter the offset between the end of this instruction and the target label, effecting the call.
Page 427 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EXTENDED LOAD WORD. Loads the value DEST, SRC of the source word operand into the wreg, [treg] destination operand. ext. indirect: (11101000) (treg) (wreg) This instruction allows you to move data from ext.
Page 428 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EXTENDED STORE WORD. Stores the SRC, DEST value of the source (leftmost) word operand wreg, [treg] into the destination (rightmost) operand. ext. indirect: (00011100) (treg) (wreg) This instruction allows you to move data from ext.
Page 429 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EXTB SIGN-EXTEND SHORT-INTEGER INTO INTEGER. Sign-extends the low-order byte EXTB wreg of the operand throughout the high-order byte (00010110) (wreg) of the operand. if DEST.7 = 1 then ←...
Page 430 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format INCB INCREMENT BYTE. Increments the value of the byte operand by 1. INCB breg ← (DEST) (DEST) + 1 (00010111) (breg) PSW Flag Settings ↑ — JUMP IF BIT IS CLEAR. Tests the specified bit.
Page 431 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF CARRY FLAG IS SET. Tests the carry flag. If the carry flag is clear, control cadd passes to the next sequential instruction. If (11011011) (disp) the carry flag is set, this instruction adds to...
Page 432 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF SIGNED GREATER THAN. Tests both the zero flag and the negative flag. If cadd either flag is set, control passes to the next (11010010) (disp) sequential instruction. If both flags are clear, this instruction adds to the program counter the offset between the end of this instruction NOTE: The displacement (disp) is sign-...
Page 433 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF SIGNED LESS THAN. Tests the negative flag. If the flag is clear, control cadd passes to the next sequential instruction. If (11011110) (disp) the negative flag is set, this instruction adds...
Page 434 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF NOT HIGHER (UNSIGNED). Tests both the zero flag and the carry flag. If the cadd carry flag is set and the zero flag is clear, (11010001) (disp) control passes to the next sequential instruction.
Page 435 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JNVT JUMP IF OVERFLOW-TRAP FLAG IS CLEAR. Tests the overflow-trap flag. If the JNVT cadd flag is set, this instruction clears the flag and (11010100) (disp) passes control to the next sequential instruction.
Page 436 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS SET. Tests the overflow-trap flag. If the flag is clear, cadd control passes to the next sequential (11011100) (disp) instruction. If the overflow-trap flag is set, this instruction clears the flag and adds to the program counter the offset between the end NOTE: The displacement (disp) is sign-...
Page 437 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format LOAD BYTE. Loads the value of the source DEST, SRC byte operand into the destination operand. breg, baop ← (DEST) (SRC) (101100aa) (baop) (breg) PSW Flag Settings —...
Page 438 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULTIPLY INTEGERS. Multiplies the source DEST, SRC (2 operands) and destination integer operands, using lreg, waop signed arithmetic, and stores the 32-bit result (11111110) (011011aa) (waop) (lreg) into the destination long-integer operand. The sticky bit flag is undefined after the instruction is executed.
Page 439 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULU MULTIPLY WORDS, UNSIGNED. Multiplies DEST, SRC (2 operands) the source and destination word operands, MULU lreg, waop using unsigned arithmetic, and stores the 32- (011011aa) (waop) (lreg) bit result into the destination double-word operand.
Page 440 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format NEGATE INTEGER. Negates the value of the integer operand. wreg ← (DEST) – (DEST) (00000011) (wreg) PSW Flag Settings ↑ — NEGB NEGATE SHORT-INTEGER. Negates the value of the short-integer operand. NEGB breg ←...
Page 441 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format COMPLEMENT WORD. Complements the value of the word operand (replaces each “1” wreg with a “0” and each “0” with a “1”). (00000010) (wreg) ← (DEST) NOT (DEST) PSW Flag Settings —...
Page 442 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format POP WORD. Pops the word on top of the stack and places it at the destination waop operand. (110011aa) (waop) ← (DEST) (SP) ← SP + 2 PSW Flag Settings —...
Page 443 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format PUSHA PUSH ALL. This instruction is used instead of PUSHF, to support the eight additional PUSHA interrupts. It pushes two words — (11110100) PSW/INT_MASK and INT_MASK1/WSR — onto the stack.
Page 444 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format RESET SYSTEM. Initializes the PSW to zero, the PC to 2080H (FF2080H in 1-Mbyte mode), and the pins and SFRs to their reset (11111111) values. Executing this instruction causes the RESET# pin to be pulled low for 16 state times.
Page 445 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHIFT WORD LEFT. Shifts the destination word operand to the left as many times as wreg,#count specified by the count operand. The count (00001001) (count) (wreg) may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H –...
Page 446 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHLL SHIFT DOUBLE-WORD LEFT. Shifts the destination double-word operand to the left SHLL lreg,#count as many times as specified by the count (00001101) (count) (breg) operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any SHLL...
Page 447 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRA ARITHMETIC RIGHT SHIFT WORD. Shifts the destination word operand to the right as SHRA wreg,#count many times as specified by the count (00001010) (count) (wreg) operand. The count may be specified either...
Page 448 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRAL ARITHMETIC RIGHT SHIFT DOUBLE- WORD. Shifts the destination double-word SHRAL lreg,#count operand to the right as many times as (00001110) (count) (lreg) specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, SHRAL...
Page 449 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRL LOGICAL RIGHT SHIFT DOUBLE-WORD. Shifts the destination double-word operand to SHRL lreg,#count the right as many times as specified by the (00001100) (count) (lreg) count operand. The count may be specified...
Page 450 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format STORE WORD. Stores the value of the SRC, DEST source (leftmost) word operand into the wreg, waop destination (rightmost) operand. (110000aa) (waop) (wreg) ← (DEST) (SRC) PSW Flag Settings —...
Page 451 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SUBB SUBTRACT BYTES. Subtracts the source DEST, SRC (2 operands) byte operand from the destination byte SUBB breg, baop operand, stores the result in the destination (011110aa) (baop) (breg) operand, and sets the carry flag as the complement of borrow.
Page 452 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format TIJMP TABLE INDIRECT JUMP. Causes execution to continue at an address selected from a TIJMP TBASE, [INDEX], #MASK table of addresses. (11100010) [INDEX] (#MASK) (TBASE) The TIJMP instruction reduces the interrupt response time associated with servicing multiple interrupt sources that are multiplexed NOTE: TIJMP multiplies OFFSET by two...
Page 453 8XC196NT USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format TRAP SOFTWARE TRAP. This instruction causes an interrupt-call that is vectored through TRAP location FF2010H. The operation of this (11110111) instruction is not affected by the state of the interrupt enable flag (I) in the PSW.
Page 454 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format LOGICAL EXCLUSIVE-OR WORDS. XORs DEST, SRC the source word operand with the destination wreg, waop word operand and stores the result in the (100001aa) (waop) (wreg) destination operand. The result has ones in the bit positions in which either operand (but not both) had a “1”...
Page 455 8XC196NT USER’S MANUAL Table A-7. Instruction Opcodes Hex Code Instruction Mnemonic SKIP XCH Direct SHRA XCH Indexed SHRL SHLL SHRAL NORML Reserved CLRB NOTB NEGB XCHB Direct DECB EXTB INCB SHRB SHLB SHRAB XCHB Indexed EST Indirect EST Indexed ESTB Indirect ESTB Indexed 20–27...
Page 456 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ADD Direct (3 ops) ADD Immediate (3 ops) ADD Indirect (3 ops) ADD Indexed (3 ops) SUB Direct (3 ops) SUB Immediate (3 ops) SUB Indirect (3 ops) SUB Indexed (3 ops) MULU Direct (3 ops) MULU Immediate (3 ops)
Page 457 8XC196NT USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic MULU Immediate (2 ops) MULU Indirect (2 ops) MULU Indexed (2 ops) ANDB Direct (2 ops) ANDB Immediate (2 ops) ANDB Indirect (2 ops) ANDB Indexed (2 ops)
Page 458 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic XORB Indexed CMPB Direct CMPB Immediate CMPB Indirect CMPB Indexed DIVUB Direct DIVUB Immediate DIVUB Indirect DIVUB Indexed LD Direct LD Immediate LD Indirect LD Indexed ADDC Direct ADDC Immediate ADDC Indirect ADDC Indexed...
Page 459 8XC196NT USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ST Direct BMOV ST Indirect ST Indexed STB Direct CMPL STB Indirect STB Indexed PUSH Direct PUSH Immediate PUSH Indirect PUSH Indexed POP Direct BMOVI POP Indirect POP Indexed...
Page 460 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic EJMP LJMP ELD Indirect ELD Indexed ELDB Indirect ELDB Indexed DPTS EPTS Reserved (Note 1) LCALL ECALL PUSHF POPF PUSHA POPA IDLPD TRAP CLRC SETC CLRVT DIV/DIVB/MUL/MULB (Note 2) NOTES: This opcode is reserved, but it does not generate an unimplemented opcode interrupt.
Page 461 8XC196NT USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic (Group I) Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode ADD (2 ops) ADD (3 ops) ADDB (2 ops)
Page 462 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Arithmetic (Group II) Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode FE 8C FE 8D FE 8E FE 8F DIVB FE 9C FE 9D...
Page 463 8XC196NT USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Stack Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode — — POPA — — — — — — POPF —...
Page 464 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Data Extended- Direct Immediate Extended-indirect indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode EBMOVI — — — — — — — — — — ELDB — — —...
Page 465 8XC196NT USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Jump Extended- Direct Immediate Extended-indirect indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode — — — — — — EJMP — — — — — — Indirect...
Page 466 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Conditional Jump Indexed Direct Immediate Indirect (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode DJNZ — — — — — — 3/— DJNZW — — —...
Page 467 8XC196NT USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Shift Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode NORML — — — — — — — — — — — — SHLB —...
Page 468 INSTRUCTION SET REFERENCE Table A-9 lists instructions alphabetically within groups, along with their execution times, ex- pressed in state times. Table A-9. Instruction Execution Times (in State Times) Arithmetic (Group I) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg.
Page 469 8XC196NT USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Arithmetic (Group II) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem. DIVB DIVU DIVUB MUL (2 ops) MUL (3 ops)
Page 470 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Stack (Register) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem. — POPA — — — — — — — —...
Page 471 8XC196NT USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Data Mnemonic Extended-indirect (Normal) EBMOVI register/register 8 + 14 per word + 16 per interrupt memory/register 8 + 17 per word + 16 per interrupt memory/memory 8 + 20 per word + 16 per interrupt...
Page 472 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Jump Mnemonic Direct Immed. Extended-indirect Extended-indexed Normal Autoinc. — — — — EJMP — — — — Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long — — —...
Page 473 8XC196NT USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Call (Memory) Extended-indirect Mnemonic Direct Immed. Extended-indexed Normal Autoinc. ECALL 1-Mbyte mode — — — — Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long LCALL 1-Mbyte mode —...
Page 474 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Conditional Jump Mnemonic Short-Indexed DJNZ 5 (jump not taken), 9 (jump taken) DJNZW 6 (jump not taken), 10 (jump taken) 5 (jump not taken), 9 (jump taken) 5 (jump not taken), 9 (jump taken) 4 (jump not taken), 8 (jump taken) 4 (jump not taken), 8 (jump taken) 4 (jump not taken), 8 (jump taken)
Page 475 8XC196NT USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Special Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long CLRC — — — — — CLRVT — — — — — — — — — — —...
Page 476 Signal Descriptions...
Page 478 SLPADDR/SLPALE SLPALE FUNCTIONAL GROUPINGS OF SIGNALS Table B-2 lists the signals for the 8XC196NT, grouped by function. A diagram of each package that is currently available shows the pin location of each signal. NOTE As new packages are supported, they will be added to the datasheets first. If your package type is not shown in this appendix, refer to the latest datasheet to find the pin locations.
Page 479 8XC196NT USER’S MANUAL Table B-2. 8XC196NT Signals Arranged by Functional Categories Programming Input/Output Input/Output (Cont’d) Bus Control & Status Control EPORT.3:0 P6.6/SC1 AINC# ALE/ADV# P0.7:4/ACH7:4 P6.7/SD1 CPVER BHE#/WRH# P1.0/EPA0/T2CLK PACT# BREQ# P1.1/EPA1 Processor Control PALE# BUSWIDTH P1.2/EPA2/T2DIR PBUS.15:0 CLKOUT P1.7:3/EPA7:3 EXTINT PMODE.3:0...
Page 480 AD6 / P3.6 / PBUS.6 / SLP6 P0.6 / ACH6 / PMODE.2 AD5 / P3.5 / PBUS.5 / SLP5 P0.5 / ACH5 / PMODE.1 AD4 / P3.4 / PBUS.4 / SLP4 P0.4 / ACH4 / PMODE.0 A2105-03 Figure B-1. 8XC196NT 68-lead PLCC Package...
Page 481 8XC196NT USER’S MANUAL SIGNAL DESCRIPTIONS Table B-3 defines the columns used in Table B-4, which describes the signals. Table B-3. Description of Columns of Table B-4 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there are more entries in this column than there are pins.
Page 482 SIGNAL DESCRIPTIONS Table B-4. Signal Descriptions (Continued) Name Type Description ADV# Address Valid This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes.
Page 483 8XC196NT USER’S MANUAL Table B-4. Signal Descriptions (Continued) Name Type Description BREQ# Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. The device can assert BREQ# at the same time as or after it asserts HLDA#.
Page 484 SIGNAL DESCRIPTIONS Table B-4. Signal Descriptions (Continued) Name Type Description EPA9:0 Event Processor Array (EPA) Input/Output pins These are the high-speed input/output pins for the EPA capture/compare channels. For high-speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared output pin (see “Generating a High-speed PWM Output”...
Page 485 INTOUT# immediately. However, if the 8XC196NT is executing code from external memory, it asserts BREQ# and waits until the external device deasserts HOLD# to assert INTOUT#. If the 8XC196NT is executing code from external memory and it receives an interrupt request as it is going into hold...
Page 486 SIGNAL DESCRIPTIONS Table B-4. Signal Descriptions (Continued) Name Type Description P2.7:0 Port 2 This is a standard bidirectional port that is multiplexed with individually selectable special-function signals. P2.6 is multiplexed with the ONCE# function. If this pin is held low during reset, the device will enter ONCE mode, so exercise caution if you use this pin for input.
Page 487 8XC196NT USER’S MANUAL Table B-4. Signal Descriptions (Continued) Name Type Description PBUS.15:0 Address/Command/Data Bus During slave programming, ports 3 and 4 serve as a bidirectional port with open-drain outputs to pass commands, addresses, and data to or from the device. Slave programming requires external pull-up resistors.
Page 488 SIGNAL DESCRIPTIONS Table B-4. Signal Descriptions (Continued) Name Type Description RESET# Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode.
Page 489 8XC196NT USER’S MANUAL Table B-4. Signal Descriptions (Continued) Name Type Description T1CLK Timer 1 External Clock External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode.
Page 490 SIGNAL DESCRIPTIONS Table B-4. Signal Descriptions (Continued) Name Type Description Write The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0 selects WRL#. This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes.
Page 491 8XC196NT USER’S MANUAL DEFAULT CONDITIONS Table B-6 lists the default functions of the I/O and control pins of the 8XC196NT with their val- ues during various operating conditions. Table B-5 defines the symbols used to represent the pin status. Refer to the DC Characteristics table in the datasheet for actual specifications for V , and V Table B-5.
Page 492 SIGNAL DESCRIPTIONS Table B-6. 8XC196NT Pin Status (Continued) Multiplexed Status During Status During Status During Port Pins With Reset Idle Powerdown P6.3 T1DIR (Note 3) (Note 3) P6.4 (Note 3) (Note 3) P6.5 (Note 3) (Note 3) P6.6 (Note 3) (Note 3) P6.7...
Page 494 Registers...
Page 496 APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-1 lists the mod- ules and major components of the device with their related configuration and status registers. Ta- ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names, addresses, and reset values.
Page 497 8XC196NT USER’S MANUAL Table C-2. Register Name, Address, and Reset Status Binary Reset Value Register Register Name Mnemonic Address High AD_COMMAND A/D Command 1FACH 1100 0000 AD_RESULT A/D Result 1FAAH 0111 1111 1100 0000 AD_TEST A/D Test 1FAEH 1100 0000...
Page 498 REGISTERS Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Address High EPA7_CON EPA Capture/Comp 7 Control 1F7CH 0000 0000 EPA7_TIME EPA Capture/Comp 7 Time 1F7EH 0000 0000 0000 0000 EPA8_CON EPA Capture/Comp 8 Control 1F80H 0000 0000...
Page 499 8XC196NT USER’S MANUAL Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Address High P6_PIN Port 6 Pin Input 1FD7H XXXX XXXX P6_REG Port 6 Data Output 1FD5H 1111 1111 PPW (or SP_PPW)
Page 500 0 = EPA initiates conversion ACH2:0 A/D Channel Selection Write the A/D conversion channel number to these bits. The 8XC196NT has four A/D channel inputs, numbered 4–7. NOTES: While a threshold-detection mode is selected for an analog input pin, no other conversion can be started.
Page 501 8 state times. 1 = A/D conversion is in progress 0 = A/D is idle ACH2:0 A/D Channel Number These bits indicate the A/D channel number that was used for the conversion. The 8XC196NT has four A/D channel inputs, numbered 4–7...
Page 502 REGISTERS AD_RESULT (Write) Address: 1FAAH AD_RESULT (Write) Reset State: 7F80H The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes. REFV7 REFV6 REFV5 REFV4 REFV3 REFV2 REFV1 REFV0 —...
Page 503 8XC196NT USER’S MANUAL AD_TEST Address: 1FAEH AD_TEST Reset State: The A/D test (AD_TEST) register enables conversions on ANGND and V and specifies adjustments for DC offset errors. Its functions allow you to perform two conversions, one on ANGND and one on V .
Page 504 REGISTERS AD_TIME Address: 1FAFH AD_TIME Reset State: The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. SAM2 SAM1 SAM0 CONV4 CONV3 CONV2 CONV1 CONV0 Function Number Mnemonic SAM2:0 A/D Sample Time These bits specify the sample time. Use the following formula to compute the sample time.
Page 505 8XC196NT USER’S MANUAL CCR0 Address: FF2018H CCR0 Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 506 REGISTERS CCR0 Address: FF2018H CCR0 (Continued) Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. LOC1 LOC0 IRC1...
Page 507 8XC196NT USER’S MANUAL CCR1 Address: FF201AH CCR1 Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit controls whether CCR2 is loaded.
Page 508 REGISTERS CCR2 Address: FF201CH CCR2 Reset State: The chip configuration register 2 (CCR2) supports extended addressing. It selects either 64-Kbyte or 1-Mbyte addressing mode and controls whether the internal OTPROM is mapped into both page 0FFH and page 00H or into page FFH only. This register is loaded from CCB2 (or PCCB2) if the LDCCB2 bit (bit 0) of CCR1 is set;...
Page 509 8XC196NT USER’S MANUAL COMPx_CON Address: Table C-3 COMP x _CON Reset State: x = 0–1 The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels. Function Number Mnemonic Time Base Select Specifies the reference timer.
Page 510 REGISTERS COMPx_CON Address: Table C-3 COMP x _CON Reset State: (Continued) The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels. Function Number Mnemonic Reset Opposite Timer Selects the timer that is to be reset if the RT bit is set. 0 = selects the reference timer for possible reset 1 = selects the opposite timer for possible reset The state of the TB bit determines which timer is the reference timer and...
Page 511 8XC196NT USER’S MANUAL COMPx_TIME Address: Table C-4 COMP x _TIME Reset State: x = 0–1 The EPA compare x time (COMP x _TIME) registers are the event-time registers for the EPA compare channels; they are functionally identically to the EPA x _TIME registers. The EPA triggers a compare event when the reference timer matches the value in COMP x _TIME.
Page 512 REGISTERS EP_DIR Address: 1FE3H EP_DIR Reset State: The extended port I/O direction (EP_DIR) register determines the I/O mode for each EPORT pin. The register settings for an open-drain output or a high-impedance input are identical. To use an open- drain output configuration, an external pull-up is required. To use a high-impedance input configu- ration, the corresponding bit in EP_REG must be set.
Page 513 8XC196NT USER’S MANUAL EP_MODE Address: 1FE1H EP_MODE Reset State: Each bit in the extended port mode (EP_MODE) register determines whether the corresponding pin functions as a standard I/O port pin or is used as an extended address port (EPORT) pin.
Page 514 REGISTERS EP_PIN Address: 1FE7H EP_PIN Reset State: The extended port input (EP_PIN) register contains the current state of each port pin, regardless of the pin mode setting. — — — — PIN3 PIN2 PIN1 PIN0 Function Number Mnemonic — Reserved; always write as zeros. PIN3:0 Extended Address Port Pin x Input This bit contains the current state of EPORT.
Page 515 8XC196NT USER’S MANUAL EP_REG Address: 1FE5H EP_REG Reset State: For pins configured as I/O pins, write the data to be driven out by output pins into the corresponding EP_REG. x bits. Set the EP_REG. x bits for input pins. For pins configured as extended-address lines, write the value of the memory page (page 00H–0FH) that is to be accessed by non-extended instruc-...
Page 516 REGISTERS EPA_MASK Address: 1FA0H EPA_MASK Reset State: 0000H The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the multiplexed EPA x interrupt EPA4 EPA5 EPA6 EPA7 EPA8 EPA9 OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVR8 OVR9 Function...
Page 517 8XC196NT USER’S MANUAL EPA_MASK1 Address: 1FA4H EPA_MASK1 Reset State: The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated with the multiplexed EPA x interrupt. — — — — COMP0 COMP1 OVRTM1 OVRTM2 Function Number Reserved; for compatibility with future devices, write zeros to these bits.
Page 518 REGISTERS EPA_PEND Address: 1FA2H EPA_PEND Reset State: 0000H When hardware detects a pending EPA x interrupt, it sets the corresponding bit in the EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
Page 519 8XC196NT USER’S MANUAL EPA_PEND1 Address: 1FA6H EPA_PEND1 Reset State: When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
Page 520 REGISTERS EPAx_CON Address: Table C-5 EPA x _CON Reset State: x = 0–9 The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit.
Page 521 8XC196NT USER’S MANUAL EPAx_CON Address: Table C-5 EPA x _CON (Continued) Reset State: x = 0–9 The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit.
Page 522 REGISTERS EPAx_CON Address: Table C-5 EPA x _CON (Continued) Reset State: x = 0–9 The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit.
Page 523 8XC196NT USER’S MANUAL EPAx_CON Table C-5. EPA x _CON Addresses and Reset Values Register Address Reset Value Register Address Reset Value EPA0_CON 1F60H EPA5_CON 1F74H EPA1_CON 1F64H FE00H EPA6_CON 1F78H EPA2_CON 1F68H EPA7_CON 1F7CH EPA3_CON 1F6CH FE00H EPA8_CON 1F80H EPA4_CON...
Page 524 REGISTERS EPAx_TIME Address: Table C-6 EPA x _TIME Reset State: x = 0–9 The EPA time (EPA x _TIME) registers are the event-time registers for the EPA channels. In capture mode, the value of the reference timer is captured in EPA x _TIME when an input transition occurs. Each event-time register is buffered, allowing the storage of two capture events at once.
Page 525 8XC196NT USER’S MANUAL EPAIPV Address: 1FA8H EPAIPV Reset State: When an EPA x interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table 10-6). EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine when EPA x is activated.
Page 526 REGISTERS INT_MASK Address: 0008H INT_MASK Reset State: The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the stack and POPF or POPA restores it.
Page 527 8XC196NT USER’S MANUAL INT_MASK1 Address: 0013H INT_MASK1 Reset State: The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
Page 528 REGISTERS INT_PEND Address: 0009H INT_PEND Reset State: When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. EPA x EPA0 EPA1...
Page 529 8XC196NT USER’S MANUAL INT_PEND1 Address: 0012H INT_PEND1 Reset State: When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
Page 530 REGISTERS IRAM_CON Address: 1FE0H IRAM_CON Reset State: The internal RAM control (IRAM_CON) register has two functions related to memory accesses. The IRAM bit allows you to control access to locations 0400–05FFH. The EA_STAT bit allows you to determine the status of the EA# pin, which controls access to locations FF2000–FF9FFFH. EA_STAT IRAM —...
Page 531 8XC196NT USER’S MANUAL ONES_REG Address: ONES_REG Reset State: FFFFH The two-byte ones register (ONES_REG) is always equal to FFFFH. It is useful as a fixed source of all ones for comparison operations. One (high byte) One (low byte) Function Number 15:0 These bits are always equal to FFFFH.
Page 532 REGISTERS Px_DIR Address: Table C-8 P x _DIR Reset State: x = 1, 2, 5, 6 Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input. The port x I/O direction (P x _DIR) register determines the I/O mode for each port x pin.
Page 533 8XC196NT USER’S MANUAL Px_MODE Address: Table C-9 P x _MODE Reset State: x = 1, 2, 5, 6 Each bit in the port x mode (P x _MODE) register determines whether the corresponding pin functions as a standard I/O port pin or is used for a special-function signal.
Page 534 REGISTERS Px_MODE Table C-10. Special-function Signals for Ports 1, 2, 5, 6 Port 1 Port 2 Special-function Signal Special-function Signal P1.0 EPA0/T2CLK P2.0 TXD/PVER P1.1 EPA1 P2.1 RXD/PALE# P1.2 EPA2/T2DIR P2.2 EXTINT/PROG# P1.3 EPA3 P2.3 BREQ# P1.4 EPA4 P2.4 INTOUT#/AINC# P1.5 EPA5 P2.5...
Page 535 8XC196NT USER’S MANUAL Px_PIN Address: Table C-11 P x _PIN Reset State: x = 0–6 The port x pin input (P x _PIN) register contains the current state of each port pin, regardless of the pin mode setting. x = 0–6...
Page 536 REGISTERS Px_REG Address: Table C-12 P x _REG Reset State: x = 1–6 P x _REG contains data to be driven out by the respective pins. When a port pin is configured as an input, the corresponding bit in P x _REG must be set. The effect of a write to P x _REG is seen on the pins only when the associated pins are configured as standard I/O port pins (P x _MODE.
Page 537 8XC196NT USER’S MANUAL P34_DRV Address: 1FF4H P34_DRV Reset State: The port 3/4 complementary enable (P34_DRV) register controls whether the port is configured as complementary or open-drain outputs. In complementary operation, Ports 3 and 4 are driven high when a one is written to the P x _REG ( x = 3–4) register. This mode does not require ports 3 and 4 to be externally pulled high by pull-up resistors.
Page 538 REGISTERS PPW (or SP_PPW) no direct access PPW (or SP_PPW) The PPW register is loaded from the external EPROM (locations 14H and 15H) in auto programming mode. The SP_PPW register is loaded from the internal test ROM in serial port programming mode. The default pulse width for serial port programming is longer than required, so you should change the value before beginning to program the device.
Page 539 8XC196NT USER’S MANUAL no direct access The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that...
Page 540 REGISTERS no direct access PSW (Continued) The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
Page 541 8XC196NT USER’S MANUAL PTSSEL Address: 0004H PTSSEL Reset State: 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine.
Page 542 REGISTERS PTSSRV Address: 0006H PTSSRV Reset State: 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre- sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt.
Page 543 8XC196NT USER’S MANUAL SBUF_RX Address: 1FB8H SBUF_RX Reset State: The serial port receive buffer (SBUF_RX) register contains data received from the serial port. The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read.
Page 544 REGISTERS SBUF_TX Address: 1FBAH SBUF_TX Reset State: The serial port transmit buffer (SBUF_TX) register contains data that is ready for transmission. In modes 1, 2, and 3, writing to SBUF_TX starts a transmission. In mode 0, writing to SBUF_TX starts a transmission only if the receiver is disabled (SP_CON.3=0).
Page 545 8XC196NT USER’S MANUAL SLP_CMD Address: 1FFAH SLP_CMD Reset State: The slave port comand (SLP_CMD) register accepts commands from the master to the slave. The commands are defined by the device software. The slave can read from and write to this register. The master can only write to it.
Page 546 REGISTERS SLP_CON Address: 1FFBH SLP_CON Reset State: The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can access the register. — — — SLPL IBEMSK OBFMSK Function Number Mnemonic — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits.
Page 547 8XC196NT USER’S MANUAL SLP_STAT Address: 1FF8H SLP_STAT Reset State: The master can read the slave port status (SLP_STAT) register to determine the status of the slave. The slave can read all bits and can write bits 7:3 for general-purpose status information. (The bits are user-defined flags.) If the master attempts to write to SLP_STAT, it actually writes to SLP_CMD.
Page 548 REGISTERS Address: Reset State: XXXXH The system’s stack pointer (SP) can point anywhere in an internal or external memory page; it must be word aligned and must always be initialized before use. The stack pointer is decremented before a PUSH and incremented after a POP, so the stack pointer should be initialized to two bytes (in 64- Kbyte mode) or four bytes (in 1-Mbyte mode) above the highest stack location.
Page 549 8XC196NT USER’S MANUAL SP_BAUD Address: 1FBCH SP_BAUD Reset State: 0000H The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.
Page 550 REGISTERS SP_CON Address: 1FBBH SP_CON Reset State: The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. — — Function Number Mnemonic — Reserved; always write as zeros. Parity Selection Bit Selects even or odd parity.
Page 551 8XC196NT USER’S MANUAL SP_STATUS Address: 1FB9H SP_STATUS Reset State: The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port. RPE/RB8 — — Function Number Mnemonic RPE/RB8 Received Parity Error/Received Bit 8 RPE is set if parity is disabled (SP_CON.2=0) and the ninth data bit received is high.
Page 552 REGISTERS SSIO_BAUD Address: 1FB4H SSIO_BAUD Reset State: The synchronous serial port baud (SSIO_BAUD) register enables and disables the baud-rate generator and selects the SSIO baud rate. During read operations, SSIO_BAUD serves as the down- counter monitor. The down-counter is decremented once every four state times when the baud-rate generator is enabled.
Page 553 8XC196NT USER’S MANUAL SSIOx_BUF (RXD, TXD) Address: Table C-14 SSIO x _BUF (RXD, TXD) Reset State: x = 0–1 The synchronous serial receive buffer x (SSIO x _BUF (RXD)) contains received data. Data is shifted into this register from the SD x pin, with the most-significant bit first.
Page 554 REGISTERS SSIOx_CON Address: Table C-15 SSIO x _CON Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 555 8XC196NT USER’S MANUAL SSIOx_CON Address: Table C-15 SSIO x _CON (Continued) Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 556 REGISTERS T1CONTROL Address: 1F98H T1CONTROL Reset State: The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 557 8XC196NT USER’S MANUAL T2CONTROL Address: 1F9CH T2CONTROL Reset State: The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 558 REGISTERS TIMERx Address: Table C-16 TIMER x Reset State: x = 1–2 The two bytes of the timer x register contain the value of timer x . This register can be written, allowing timer x to be initialized to a value other than zero. Timer Value (high byte) Timer Value (low byte) Function...
Page 559 These bits can be programmed, but cannot be erased. WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot be returned to Intel for failure analysis. — — —...
Page 560 REGISTERS WATCHDOG Address: WATCHDOG Reset State: Unless it is cleared every 64K state times, the watchdog timer resets the device. To clear the watchdog timer, send “1EH” followed immediately by “E1H” to location 0AH. Clearing this register the first time enables the watchdog with an initial value of 0000H, which is incremented once every state time.
Page 561 8XC196NT USER’S MANUAL Address: Reset State: The window selection register (WSR) has two functions. One bit enables and disables the bus-hold protocol. The remaining bits select windows. Windows map sections of RAM into the upper section of the lower register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it.
Page 562 REGISTERS Table C-17. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address † EPA_PEND 1FA2H 00E2H 00E2H 00A2H EPA_PEND1 1FA6H 00E6H 00E6H 00A6H EPA0_CON...
Page 563 8XC196NT USER’S MANUAL Table C-17. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address P2_REG 1FCDH 00EDH 00CDH 00CDH P6_DIR 1FD3H...
Page 564 REGISTERS ZERO_REG Address: ZERO_REG Reset State: 0000H The two-byte zero register (ZERO_REG) is always equal to zero. It is useful as a fixed source of the constant zero for comparisons and calculations. Zero (high byte) Zero (low byte) Function Number 15:0 Zero This register is always equal to zero.
Page 566 Glossary...
Page 568 GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between corresponding actual and ideal code transitions. Absolute error accounts for all deviations of an actual A/D converter from an ideal converter.
Page 569 8XC196NT USER’S MANUAL CCBs Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the CCBs after a device reset, unless the device is entering programming modes, in which case the PCCBs is used. CCRs Chip configuration registers. Registers that specify the environment in which the device will be operating.
Page 570 GLOSSARY DC input leakage Leakage current from an analog input pin to ground. deassert The act of making a signal inactive (disabled). The polarity (high or low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix;...
Page 571 8XC196NT USER’S MANUAL external address A 20-bit address is presented on the device pins. The address decoded by an external device depends on how many of these address lines the external system uses. See also internal address. far constants Constants that can be accessed only with extended instructions.
Page 572 GLOSSARY interrupt controller The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. Also called the programmable interrupt controller (PIC). interrupt latency The total delay between the time that an interrupt is generated (not acknowledged) and the time that the device begins executing the interrupt service routine or PTS routine.
Page 573 8XC196NT USER’S MANUAL Most-significant bit of a byte or most-significant byte of a word. n-channel FET A field-effect transistor with an n-type conducting path (channel). n-type material Semiconductor material with introduced impurities (doping) causing it to have an excess of negatively charged carriers.
Page 574 GLOSSARY OTPROM One-time-programmable read-only memory. Similar to EPROM, but it comes in an unwindowed package and cannot be erased. p-channel FET A field-effect transistor with a p-type conducting path. p-type material Semiconductor material with introduced impurities (doping) causing it to have an excess of positively charged carriers.
Page 575 8XC196NT USER’S MANUAL PTSCB See PTS control block. PTS control block A block of data required for each PTS interrupt. The microcode executes the proper PTS routine based on the contents of the PTS control block. PTS cycle The microcoded response to a single PTS interrupt request.
Page 576 GLOSSARY repeatability error difference between corresponding code transitions from different actual characteristics taken from the same converter on the same channel with the same temperature, voltage, and frequency conditions. The amount of repeatability error depends on the comparator’s ability to resolve very similar voltages and the extent to which random noise contributes to the error.
Page 577 8XC196NT USER’S MANUAL RESET# is a level-sensitive input. EXTINT is normally a sampled input; however, the powerdown circuitry uses EXTINT as a level-sensitive input during powerdown mode. Successive approximation register. A component of the A/D converter. The “1” value of a bit or the act of giving it a “1”...
Page 578 GLOSSARY successive approximation An A/D conversion method that uses a binary search to arrive at the best digital representation of an analog input. temperature coefficient Change in the stated variable for each degree Centigrade of temperature change. temperature drift The change in a specification due to a change in temperature.
Page 579 8XC196NT USER’S MANUAL wraparound The result of interpreting an address or a memory page value whose hexadecimal expression uses more bits than the number of available address lines. Wraparound ignores the upper address bits and directs access to the page value expressed by the lower bits.
Page 580 Index...
Page 582 INDEX #, defined, 1-3, A-1 zero-offset adjustment, 11-3, 11-5 1-Mbyte mode, 4-1 zero-offset error, 11-17 fetching code, 4-24, 4-26 See also port 0 fetching data, 4-27 A/D scan mode‚ See PTS incrementing SP, 4-13 A19:0, 4-1 64-Kbyte mode, 4-1, 4-5 A19:16, 6-18 fetching code, 4-24, 4-26 See also EPORT...
Page 583 8XC196NT USER’S MANUAL Analog-to-digital converter‚ See A/D converter BREQ#, 14-3, 14-19, B-6 AND instruction, A-2, A-8, A-46, A-47, A-53, Bulletin board system (BBS), 1-9 A-60 Bus contention, See address/data bus, contention ANDB instruction, A-2, A-8, A-9, A-47, A-48, Bus controller, 2-5, 14-17, 15-6...
Page 584 INDEX Carry (C) flag, 3-5, A-4, A-5, A-11, A-22, A-23, COMP1_TIME, C-66 CompuServe forums, 1-10 A-24, A-25, A-35 Cascading timers, 10-7 Conditional jump instructions, A-5 CBE flag, C-51 Constants, near, 4-24 CCB fetch, 14-5 CPU, 2-3 and BHE#, 6-13 CPVER, 15-12, B-6 and bus-width, 14-11 Customer service, 1-8 and P5.5, 6-13...
Page 585 8XC196NT USER’S MANUAL DJNZW instruction, A-2, A-5, A-15, A-50, A-57, re-enabling the compare event, 10-22, 10-25, A-65 C-14, C-26 DLE flag, 15-34, 15-35 resetting the timer in compare mode, 10-24, Documents, related, 1-5–1-7 C-27 DOUBLE-WORD, defined, 3-3 resetting the timers, 10-23, 10-26, C-15, C-27...
Page 586 INDEX and external address, 14-1 and inhibiting interrupts, 5-8 block diagram, 6-20 Floating point library, 3-5 complementary output mode, 6-21 Formulas configuration register settings, 6-24 A/D conversion result, 11-9, 11-14 configuring pins, 6-24 A/D conversion time, 11-7 for extended-address, 6-24 A/D error, 11-12 for I/O, 6-24 A/D sample time, 11-7...
Page 587 8XC196NT USER’S MANUAL slave programming circuit, 15-16 differences, 3-5 UPROM considerations, 15-7 execution times, A-59–A-60 HLDA#, 14-4, 14-19, B-7 lengths, A-52–A-59 considerations, 6-12 opcode map, A-2–A-3 HLDEN bit, 4-16, 14-21 opcodes, A-46–A-51 Hold latency, See bus-hold protocol overview, 3-1–3-5 HOLD#, 14-4, 14-19, B-7 protected instructions, 5-8 reference, A-1–A-3...
Page 588 INDEX JH instruction, A-3, A-5, A-23, A-50, A-57, A-65 Memory partitions JLE instruction, A-3, A-5, A-23, A-50, A-57, A-65 OTPROM, 15-2 JLT instruction, A-3, A-5, A-24, A-50, A-57, A-65 program memory, 15-2 JNC instruction, A-2, A-5, A-24, A-50, A-57, special-purpose memory, 15-2 A-65 Memory protection, 15-3–15-7 JNE instruction, A-2, A-5, A-24, A-50, A-57, A-65...
Page 589 8XC196NT USER’S MANUAL NMI, 5-3, 5-4, 5-6, B-8 memory map, 15-2 and bus-hold protocol, 14-22 programming, 15-1–15-44 hardware considerations, 5-6 See also programming modes idle, powerdown, reset status, B-15 ROM-dump mode, 15-30 Noise, reducing, 6-2, 6-3, 6-6, 11-3, 11-13, 11-14,...
Page 590 INDEX PACT#, B-9 structure, 6-7 See also EPA Pages (memory), 4-1, 4-2 page 00H, 4-3 Port 2, 2-8, 13-2, B-9 page 0FH, 4-2 considerations, 6-11 page FFH, 4-2, 4-26 idle, powerdown, reset status, B-14 accessing, 4-23 initializing, 6-9 page number and EPORT, 4-24 logic tables, 6-8 operation, 6-3, 6-8 PALE#, 15-8, 15-10, 15-12, B-9...
Page 591 8XC196NT USER’S MANUAL overview, 6-1 A/D scan mode, 5-26–5-31 pin configuration, 6-9, 6-11 and A/D converter, 5-26, 5-27 example, 6-10 and EPA, 5-31–5-41 SFRs, 6-5, 10-4, 10-5 and SSIO handshaking, 8-6 structure, 6-7 and SSIO port, 8-5, 8-6 See also EPA‚ SSIO ports block transfer mode, 5-24 Port, serial‚...
Page 592 INDEX register RAM, 4-13 P2_REG, 7-3 considerations, 6-12 RD#, 14-4, B-10 considerations, 6-12 P34_DRV, 6-15, 6-17 during bus hold, 14-19 P3_PIN, 9-2, 9-5 idle, powerdown, reset status, B-14 P3_REG, 9-2, 9-5 READY, 14-5, 14-17–14-19, 15-25, B-10 P5_MODE and wait states, 14-17 considerations, 6-12, 6-13 P6_DIR, 7-3 considerations, 6-13...
Page 593 8XC196NT USER’S MANUAL and bus-hold protocol, 14-23 SBUF_TX, C-68 and CCB fetches, 4-8 SC0, 8-5, B-11 and operating mode selection, 4-24 configuring for handshaking, 8-6 circuit diagram, 12-11 SC1, 8-5, B-11 status configuring for handshaking, 8-6 CLKOUT/P2.7, 6-6, 6-12 SCALL instruction, A-3, A-35, A-46, A-52, A-56,...
Page 594 INDEX SIO port, 2-8, 7-1 interrupts, 9-8, 9-16 CBF interrupt, 9-16 9-bit data‚ See mode 2‚ mode 3 block diagram, 7-1, 10-2 IBF interrupt, 9-16 calculating baud rate, 7-10, 7-11, C-54 OBE interrupt, 9-16 downloading to OTPROM‚ See serial port modes, 9-8–9-13 programming mode overview, 9-2–9-5...
Page 595 8XC196NT USER’S MANUAL and PTS, 8-6 and EPAx interrupt, 10-29, 10-31 block diagram, 8-1 Timer, watchdog‚ See watchdog timer configuring port pins, 8-9 Timer/counters, 2-9, 10-6, 10-7 enabling interrupts, 8-13 and PWM, 10-14, 10-15, 10-16 handshaking, 8-6, 8-7 cascading, 10-7...
Page 596 INDEX programming, 15-6–15-7 XCHB instruction, A-2, A-3, A-44, A-46, A-55, USFR, 15-7 A-62 XOR instruction, A-2, A-45, A-48, A-53, A-60 XORB instruction, A-2, A-45, A-48, A-49, A-53, A-60 , 12-1, B-12 XTAL1, 12-2, B-13 and programming modes, 15-14 and Miller effect, 12-8 , 12-1, 13-2, 15-13, B-12 and programming modes, 15-13, 15-31 and programming modes, 15-14...