Interrupt Signals And Registers - Intel 8XC196K Series User Manual

5.2

INTERRUPT SIGNALS AND REGISTERS

Table 5-1 describes the external interrupt signals and Table 5-2 describes the control and status
registers for both the interrupt controller and PTS.
PWM Signal Port Pin
EXTINT P2.2
†
NMI —
†
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
Table 5-2. Interrupt and PTS Control and Status Registers
Register Register
Mnemonic Name
CAN_INT 1E5FH
(CA only)
Table 5-1. Interrupt Signals
Type
I External Interrupt
In normal operating mode, a rising edge on EXTINT sets the
EXTINT interrupt pending flag. EXTINT is sampled during
phase 2 (CLKOUT high). The minimum high time is one state
time.
If the chip is in idle mode and if EXTINT is enabled, a rising
edge on EXTINT brings the chip back to normal operation,
where the first action is to execute the EXTINT service
routine. After completion of the service routine, execution
resumes at the the IDLPD instruction following the one that
put the device into idle mode.
In powerdown mode, asserting EXTINT causes the chip to
return to normal operating mode. If EXTINT is enabled, the
EXTINT service routine is executed. Otherwise, execution
continues at the instruction following the IDLPD instruction
that put the device into powerdown mode.
I Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI causes a
vector through the NMI interrupt at location 203EH. NMI must
be asserted for greater than one state time to guarantee that
it is recognized.
In idle mode, a rising edge on the NMI pin causes the device
to return to normal operation, where the first action is to
execute the NMI service routine. After completion of the
service routine, execution resumes at the instruction following
the IDLPD instruction that put the device into idle mode.
In powerdown mode, a rising edge on the NMI pin does not
cause the device to exit powerdown.
CAN Interrupt Pending
This read-only register indicates the source of the highest-priority
pending CAN interrupt.
STANDARD AND PTS INTERRUPTS
Description
Description
5-3