Intel 8XC196K Series User Manual page 146

Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports
use Schmitt-triggered buffers for improved noise immunity. Port 5 uses a standard input buffer
because of the high speeds required for system control functions. The signals are latched into the
Px_PIN sample latch and output onto the internal bus when the Px_PIN register is read.
The falling edge of RESET# turns on transistor Q3, which remains on for about 300 ns, causing
the pin to change rapidly to its reset state. The active-low level of RESET# turns on transistor Q4,
which weakly holds the pin high. (Q4 can source approximately –10 µA; consult the datasheet
for exact specifications.) Q4 remains on, weakly holding the pin high, until your software writes
to the Px_MODE register.
P2.7 is an exception. After reset, P2.7 carries the CLKOUT signal (half the
crystal input frequency) rather than being held high. When CLKOUT is
selected, it is always a complementary output.
NOTE (8XC196CA, JQ, JR, JT, JV, KQ, KR)
I/O PORTS
6-7