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T1CONTROL
The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count
rate for timer 1.
7
CE
UD
Bit
Bit
Number
Mnemonic
7
CE
6
UD
5:3
M2:0
2:0
P2:0
M2
M1
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0)
0 = count down
1 = count up
EPA Clock Direction Mode Bits
These bits determine the timer clocking source and direction control
source.
M2
M1
M0
Clock Source
0
0
0
F
/4
OSC
X
0
1
T1CLK Pin
0
1
0
F
/4
OSC
0
1
1
T1CLK Pin
1
1
1
quadrature clocking using T1CLK and T1DIR pins
†
If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
††
These modes are reserved on the 8XC196CA, J x devices.
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2
P1
P0
Prescaler
0
0
0
divide by 1 (disabled)
0
0
1
divide by 2
0
1
0
divide by 4
0
1
1
divide by 8
1
0
0
divide by 16
1
0
1
divide by 32
1
1
0
divide by 64
1
1
1
reserved
Address:
Reset State:
M0
P2
Function
Direction Source
UD bit (T1CONTROL.6)
†
UD bit (T1CONTROL.6)
††
T1DIR Pin
†
††
T1DIR Pin
Resolution (at 16 MHz)
250 ns
500 ns
1 µs
2 µs
4 µs
8 µs
16 µs
—
REGISTERS
T1CONTROL
1F98H
00H
0
P1
P0
††
††
C-75
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