Intel 8XC196K Series User Manual page 539

Table of Contents

8XC196K x, J x , CA USER'S MANUAL

Program the CAN bit timing 1 (CAN_BTIME1) register to define the sample time and the sample

mode. The CAN controller samples the bus during the last one (in single-sample mode) or three (in

three-sample mode) time quanta of t

Therefore, specifying the lengths of t

mission point.

The CCE bit (CAN_CON.6) must be set to enable write access to this register.

For correct operation according to the CAN protocol, the total bit time length must be at least 8

time quanta, so the sum of the programmed values of TSEG1 and TSEG2 must be at least 5.

(The total bit time is the sum of t

quanta, and the hardware adds 1 to both TSEG1 and TSEG2. Therefore, if TSEG1 + TSEG2 =

5, the total bit length will be equal to 8 (1+5+1+1)).

, and initiates a transmission at the end of t

Sampling Mode

This bit determines how many samples are taken to determine a valid bit

1 = 3 samples, using majority logic

0 = 1 sample

Time Segment 2

This field determines the length of time that follows the sample point within

a bit time. Valid programmed values are 1–7; the hardware adds 1 to this

value. (Note 2)

Time Segment 1

This field defines the length of time that precedes the sample point within a

bit time. Valid programmed values are 2–15; the hardware adds 1 to this

value. In three-sample mode, the hardware adds 2 time quanta to allow

time for the two additional samples. (Note 2)

Reset State:

defines both the sample point and the trans-

. The length of t