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8XC196K x , J x , CA USER'S MANUAL
Figure 15-11 shows an 8-bit system with both flash and RAM. The flash is the lower half of mem-
ory, and the RAM is the upper half. This system configuration uses the most-significant address
bit (AD15) as the chip-select signal and ALE as the address-latch signal.
AD15
AD14:8
ALE
8XC196
AD7:0
RD#
WR#
Applies to the 8XC196KS, KT devices in bus timing modes 1 and 2 only.
15-22
A14:8
74AC
373
LE
LE
A7:0
74AC
373
Figure 15-11. 8-bit System with Flash and RAM
CS#
A14:8
D7:0
32K×8
Flash
(28F256)
A7:0
OE#
CS#
A12:8
D7:0
8K×8
RAM
A7:0
OE#
WE#
A3078-01
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