Intel 8XC196K Series User Manual page 498

Table A-9. Instruction Execution Times (in State Times) (Continued)
Mnemonic
NORML
SHL
SHLB
SHLL
SHR
SHRA
SHRAB
SHRAL
SHRB
SHRL
Mnemonic
CLRC
CLRVT
DI
EI
IDLPD
Valid key
Invalid key
NOP
RST
SETC
SKIP
Mnemonic
DPTS
EPTS
NOTE: The column entitled "Reg." lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled "Mem." lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 4-1 on page 4-2 for address information.
Direct
8 + 1 per shift (9 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
Special
Direct Immed.
Normal
2 —
2 —
2 —
2 —
— 12
— 28
2 —
4 —
2 —
3 —
Direct Immed.
Normal
2 —
2 —
INSTRUCTION SET REFERENCE
Shift
Indirect
Autoinc.
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
PTS
Indirect
Autoinc.
— —
— —
Indexed
Short Long
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
Indexed
Short Long
— —
— —
A-59