User Manuals: Intel 8XC196JT Microcontroller

Manuals and User Guides for Intel 8XC196JT Microcontroller. We have 1 Intel 8XC196JT Microcontroller manual available for free PDF download: User Manual

Intel 8XC196JT User Manual (651 pages)

Brand: Intel | Category: Microcontrollers | Size: 3 MB

Table of Contents
4
Guide to this Manual
22
Manual Contents
24
Notational Conventions and Terminology
26
Related Documents
28
Electronic Support Systems
31
Faxback Service
31
Bulletin Board System (BBS)
32
How to Find Ap BUILDER Software and Hypertext Documents on the BBS
33
Compuserve Forums
33
World Wide Web
33
Technical Support
34
Product Literature
34
Training Classes
34
Architectural Overview
36
Typical Applications
38
Device Features
39
Block Diagram
39
CPU Control
41
Register File
41
Register Arithmetic-Logic Unit (RALU)
41
Code Execution
42
Instruction Format
42
Memory Controller
43
Interrupt Service
43
Internal Timing
44
Internal Peripherals
45
I/O Ports
46
Serial I/O (SIO) Port
46
Synchronous Serial I/O (SSIO) Port
46
Slave Port (8XC196K X Only)
47
Event Processor Array (EPA) and Timer/Counters
47
Analog-To-Digital Converter
48
Watchdog Timer
48
CAN Serial Communications Controller (87C196CA Only)
48
Special Operating Modes
48
Reducing Power Consumption
49
Testing the Printed Circuit Board
49
Programming the Nonvolatile Memory
49
Design Considerations for 87C196Ca Devices
50
Design Considerations for 8Xc196Jq, Jr, Jt, and Jv Devices
51
Programming Considerations
54
Overview of the Instruction Set
56
BIT Operands
57
BYTE Operands
57
SHORT-INTEGER Operands
57
WORD Operands
57
INTEGER Operands
58
DOUBLE-WORD Operands
58
LONG-INTEGER Operands
59
Converting Operands
59
Conditional Jumps
59
Floating Point Operations
59
Addressing Modes
60
Direct Addressing
61
Immediate Addressing
61
Indirect Addressing
61
Indirect Addressing with Autoincrement
62
Indirect Addressing with the Stack Pointer
62
Indexed Addressing
62
Short-Indexed Addressing
62
Long-Indexed Addressing
63
Zero-Indexed Addressing
63
Assembly Language Addressing Mode Selections
64
Direct Addressing
64
Indexed Addressing
64
Software Standards and Conventions
64
Using Registers
64
Addressing 32-Bit Operands
65
Linking Subroutines
65
Software Protection Features and Guidelines
66
Memory Partitions
68
External Devices (Memory or I/O)
70
Program and Special-Purpose Memory
70
Program Memory
72
Special-Purpose Memory
72
Reserved Memory Locations
73
Interrupt and PTS Vectors
73
Security Key
73
Chip Configuration Bytes (Ccbs)
73
Special-Function Registers (Sfrs)
74
Memory-Mapped Sfrs
74
Peripheral Sfrs
75
Internal RAM (Code RAM)
79
Register File
79
General-Purpose Register RAM
80
Stack Pointer (SP)
80
CPU Special-Function Registers (Sfrs)
82
Windowing
82
Selecting a Window
83
Addressing a Location through a Window
86
32-Byte Windowing Example
89
Unsupported Locations Windowing Example
90
Using the Linker Locator to Set up a Window
90
Windowing and Addressing Modes
92
Standard and Pts Interrupts
94
Overview
96
Interrupt Signals and Registers
98
Interrupt Sources and Priorities
99
Special Interrupts
101
Unimplemented Opcode
101
Software Trap
101
Nmi
101
External Interrupt Pins
101
Multiplexed Interrupt Sources
102
End-Of-PTS Interrupts
102
Interrupt Latency
102
Situations that Increase Interrupt Latency
103
Calculating Latency
104
Standard Interrupt Latency
104
PTS Interrupt Latency
105
Programming the Interrupts
106
Programming the Multiplexed Interrupts
106
Modifying Interrupt Priorities
109
Determining the Source of an Interrupt
111
Determining the Source of Multiplexed Interrupts
111
Initializing the Pts Control Blocks
113
Specifying the PTS Count
114
Selecting the PTS Mode
116
Single Transfer Mode
116
Block Transfer Mode
119
A/D Scan Mode
121
A/D Scan Mode Cycles
124
A/D Scan Mode Example 1
124
A/D Scan Mode Example 2
125
PWM Modes
126
PWM Toggle Mode Example
127
PWM Remap Mode Example
132
I/O Ports
138
I/O Ports Overview
140
Input-Only Port 0
140
Standard Input-Only Port Operation
141
Standard Input-Only Port Considerations
142
Bidirectional Ports 1, 2, 5, and 6
143
Bidirectional Port Operation
145
Bidirectional Port Pin Configurations
149
Bidirectional Port Pin Configuration Example
150
Bidirectional Port Considerations
151
Design Considerations for External Interrupt Inputs
154
Bidirectional Ports 3 and 4 (Address/Data Bus)
154
Bidirectional Ports 3 and 4 (Address/Data Bus) Operation
155
Using Ports 3 and 4 as I/O
157
Design Considerations for Ports 3 and 4
158
Serial I/O (Sio) Port
160
Serial I/O (Sio) Port Functional Overview
162
Serial I/O Port Signals and Registers
163
Serial Port Modes
165
Synchronous Mode (Mode 0)
165
Asynchronous Modes (Modes 1, 2, and 3)
167
Mode 1
167
Mode 2
168
Mode 3
168
Mode 2 and 3 Timings
168
Multiprocessor Communications
169
Programming the Serial Port
169
Configuring the Serial Port Pins
169
Programming the Control Register
169
Programming the Baud Rate and Clock Source
171
Enabling the Serial Port Interrupts
173
Determining Serial Port Status
174
Programming Example Using an Interrupt-Driven Routine
175
Synchronous Serial I/O (Ssio) Port
180
Synchronous Serial I/O (Ssio) Port Functional Overview
182
Ssio Port Signals and Registers
183
Ssio Operation
184
Ssio Handshaking
187
SSIO Handshaking Configuration
187
SSIO Handshaking Operation
188
Programming the Ssio Port
190
Configuring the SSIO Port Pins
190
Programming the Baud Rate and Enabling the Baud-Rate Generator
190
Controlling the Communications Mode and Handshaking
191
Enabling the SSIO Interrupts
194
Determining SSIO Port Status
194
Programming Considerations
194
Programming Example
196
Slave Port
198
Slave Port Functional Overview
201
Slave Port Signals and Registers
201
Hardware Connections
205
Slave Port Modes
207
Standard Slave Mode Example
207
Master Device Program
207
Slave Device Program
208
Demultiplexed Bus Timings
209
Shared Memory Mode Example (8XC196KS and KT Only)
210
Master Device Program
210
Slave Device Program
211
Multiplexed Bus Timings
212
Configuring the Slave Port
213
Enabling the Slave Port Interrupts
215
Determining Slave Port Status
215
Using Status Bits to Synchronize Master and Slave
215
Event Processor Array (Epa)
218
Epa Functional Overview
220
Epa and Timer/Counter Signals and Registers
221
Timer/Counter Functional Overview
225
Cascade Mode (Timer 2 Only)
226
Quadrature Clocking Mode
226
Epa Channel Functional Overview
228
Operating in Capture Mode
230
Handling EPA Overruns
231
Operating in Compare Mode
232
Generating a Low-Speed PWM Output
233
Generating a Medium-Speed PWM Output
234
Generating a High-Speed PWM Output
235
Generating the Highest-Speed PWM Output
235
Programming the Epa and Timer/Counters
236
Configuring the EPA and Timer/Counter Port Pins
236
Programming the Timers
236
Programming the Capture/Compare Channels
239
Programming the Compare-Only Channels
244
Enabling the Epa Interrupts
245
Determining Event Status
247
Servicing the Multiplexed Epa Interrupt with Software
248
Using the TIJMP Instruction to Reduce Interrupt Service Overhead
250
Programming Examples for Epa Channels
252
EPA Compare Event Program
252
EPA Capture Event Program
253
EPA PWM Output Program
254
Analog-To-Digital Converter
256
A/D Converter Functional Overview
258
A/D Converter Signals and Registers
259
A/D Converter Operation
260
Programming the A/D Converter
261
Programming the A/D Test Register
262
Programming the A/D Result Register (for Threshold Detection Only)
263
Programming the A/D Time Register
263
Programming the A/D Command Register
265
Enabling the A/D Interrupt
266
Determining A/D Status and Conversion Results
266
Design Considerations
267
Designing External Interface Circuitry
268
Minimizing the Effect of High Input Source Resistance
269
Suggested A/D Input Circuit
270
Analog Ground and Reference Voltages
270
Using Mixed Analog and Digital Inputs
271
Understanding A/D Conversion Errors
271
Can Serial Communications Controller
278
Can Functional Overview
280
Can Controller Signals and Registers
282
Can Controller Operation
283
Address Map
284
Message Objects
284
Receive and Transmit Priorities
285
Message Acceptance Filtering
285
Message Frames
286
Error Detection and Management Logic
288
Bit Timing
289
Bit Timing Equations
291
Configuring the Can Controller
292
Programming the CAN Control (CAN_CON) Register
292
Programming the Bit Timing 0 (CAN_BTIME0) Register
294
Programming the Bit Timing 1 (CAN_BTIME1) Register
295
Programming a Message Acceptance Filter
297
Configuring Message Objects
299
Specifying a Message Object's Configuration
300
Programming the Message Object Identifier
301
Programming the Message Object Control Registers
302
Message Object Control Register 0
302
Message Object Control Register 1
302
Programming the Message Object Data
302
Enabling the Can Interrupts
308
Determining the Can Controller's Interrupt Status
311
Flow Diagrams
314
Design Considerations
320
Hardware Reset
320
Software Initialization
320
Bus-Off State
320
Minimum Hardware Considerations
322
Minimum Connections
324
Unused Inputs
325
I/O Port Pin Connections
325
Applying and Removing Power
327
Noise Protection Tips
327
Providing the Clock
328
Using the On-Chip Oscillator
328
Using a Ceramic Resonator Instead of a Crystal Oscillator
330
Providing an External Clock Source
330
Resetting the Device
331
Generating an External Reset
333
Issuing the Reset (RST) Instruction
335
Issuing an Illegal IDLPD Key Operand
335
Enabling the Watchdog Timer
335
Detecting Oscillator Failure
335
Special Operating Modes
336
Special Operating Mode Signals and Registers
338
Reducing Power Consumption
340
Idle Mode
340
Powerdown Mode
341
Enabling and Disabling Powerdown Mode
341
Entering Powerdown Mode
342
Exiting Powerdown Mode
342
Generating a Hardware Reset
343
Asserting the External Interrupt Signal
343
Once Mode
346
Entering and Exiting ONCE Mode
346
Reserved Test Modes
347
Interfacing with External Memory
348
External Memory Interface Signals
350
Chip Configuration Registers and Chip Configuration Bytes
353
Bus Width and Multiplexing
357
Timing Requirements for BUSWIDTH
359
16-Bit Bus Timings
360
8-Bit Bus Timings
362
Wait States (Ready Control)
363
Bus-Hold Protocol (8Xc196Kq, Kr, Ks, Kt Only)
366
Enabling the Bus-Hold Protocol (8XC196K X Only)
367
Disabling the Bus-Hold Protocol (8XC196K X Only)
368
Hold Latency (8XC196K X Only)
368
Regaining Bus Control (8XC196K X Only)
369
Bus-Control Modes
369
Standard Bus-Control Mode
369
Write Strobe Mode
373
Address Valid Strobe Mode
375
Address Valid with Write Strobe Mode
378
Bus Timing Modes (8Xc196Ks, Kt Only)
379
Mode 3, Standard Mode
381
Mode 0, Standard Timing with One Automatic Wait State
381
Mode 1, Long Read/Write Mode
381
Mode 2, Long Read/Write with Early Address
382
Design Considerations
383
System Bus Ac Timing Specifications
385
Programming the Nonvolatile Memory
390
Programming Methods
393
Otprom Memory Map
393
Security Features
394
Controlling Access to Internal Memory
395
Controlling Access to the OTPROM During Normal Operation
395
Controlling Access to the OTPROM During Programming Modes
396
Controlling Fetches from External Memory
397
Enabling the Oscillator Failure Detection Circuitry
399
Programming Pulse Width
399
Modified Quick-Pulse Algorithm
401
Programming Mode Pins
402
Entering Programming Modes
405
Selecting the Programming Mode
405
Power-Up and Power-Down Sequences
405
Power-Up Sequence
406
Power-Down Sequence
406
Slave Programming Mode
406
Reading the Signature Word and Programming Voltages
407
Slave Programming Circuit and Memory Map
407
Operating Environment
409
Slave Programming Routines
411
Timing Mnemonics
416
Auto Programming Mode
417
Auto Programming Circuit and Memory Map
417
Operating Environment
419
Auto Programming Routine
419
Auto Programming Procedure
421
ROM-Dump Mode
422
Serial Port Programming Mode
423
Serial Port Programming Circuit and Memory Map
423
Changing Serial Port Programming Defaults
425
Executing Programs from Internal RAM
426
Reduced Instruction Set Monitor (RISM)
426
RISM Command Descriptions
427
RISM Command Examples
429
Example 1 - Programming the PPW
430
Example 2 - Reading OTPROM Contents
431
Example 3 - Loading a Program into Internal RAM
431
Example 4 - Setting the PC and Executing the Program
433
Writing to OTPROM with Examples 3 and 4
434
Run-Time Programming
435
Instruction Set Reference
438

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Intel 8XC196JT User Manual (651 pages)

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