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PSW (Continued)
The processor status word (PSW) actually consists of two bytes. The high byte is the status word,
which is described here; the low byte is the INT_MASK register. The status word contains one bit
(PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that
enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the
state of a user's program.
The status word portion of the PSW cannot be accessed directly. To access the status word, push the
value onto the stack (PUSHF), then pop the value to a register (POP test_reg ). The PUSHF and
PUSHA instructions save the PSW in the system stack and then clear it; POPF and POPA restore it.
15
Z
N
7
Bit
Bit
Number
Mnemonic
2
PSE
1
I
0
ST
V
VT
See INT_MASK on page C-46
PTS Enable
This bit globally enables or disables the peripheral transaction server
(PTS). The EPTS instruction sets this bit; DPTS clears it.
1 = enable PTS
0 = disable PTS
Interrupt Disable (Global)
This bit globally enables or disables the servicing of all maskable
interrupts . The bits in INT_MASK and INT_MASK1 individually enable or
disable the interrupts. The EI instruction sets this bit; DI clears it.
1 = enable interrupt servicing
0 = disable interrupt servicing
Sticky Bit Flag
This flag is set to indicate that, during a right shift, a "1" was shifted into
the carry flag and then shifted out. It can be used with the carry flag to
allow finer resolution in rounding decisions.
C
PSE
Function
REGISTERS
PSW
no direct access
8
I
ST
0
C-59
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