Intel 8XC196K Series User Manual page 355

8XC196K x , J x , CA USER'S MANUAL
CCR0 (Continued)
The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal
memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus
width.
7
LOC1 LOC0
Bit Bit
Number Mnemonic
3 ALE
2 WR
1 BW0
0 PD
Figure 15-1. Chip Configuration 0 (CCR0) Register (Continued)
15-6
IRC1 IRC0
Address Valid Strobe and Write Strobe
These bits define which bus-control signals will be generated during
external read and write cycles.
ALE WR
0 0 address valid with write strobe mode
(ADV#, RD#, WRL#, WRH#)
0 1 address valid strobe mode
(ADV#, RD#, WR#, BHE#)
1 0 write strobe mode
(ALE, RD#, WRL#, WRH#)
1 1 standard bus-control mode
(ALE, RD#, WR#, BHE#)
†
On the 8XC196J x device, the BHE#/WRH# pin is not implemented.
Buswidth Control
This bit, along with the BW1 bit (CCR1.2), selects the bus width.
BW1 BW0
0 0 illegal
0 1 16-bit only
1 0 8-bit only
1 1 BUSWIDTH pin controlled
†
This mode is unavailable on the 87C196CA, 8XC196J x devices. The
BUSWIDTH pin is not implemented.
Powerdown Enable
Controls whether the IDLPD #2 instruction causes the device to enter
powerdown mode. Clearing this bit at reset can prevent accidental entry
into powerdown mode.
1 = enable powerdown mode
0 = disable powerdown mode
Address:
Reset State:
ALE WR
Function
†
†
†
†
†
2018H
XXH
0
BW0 PD