Ssio Port Signals And Registers - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
8.2

SSIO PORT SIGNALS AND REGISTERS

Table 8-1 describes the SSIO signals and Table 8-2 describes the control and status registers.
SSIO
Port
Port
Pin Signal Type
Signal
P6.4 SC0
P6.5 SD0
P6.6 SC1
P6.7 SD1
Table 8-2. SSIO Port Control and Status Registers
Mnemonic Address
INT_MASK1
NOTE: Always write zeros to the reserved bits in these registers.
8-2
Table 8-1. SSIO Port Signals
SSIO Port
I/O SSIO0 Clock Pin
This pin transmits a clock signal when SSIO0 is configured as a
master and receives a clock signal when it is configured as a
slave.
SC0 carries a clock signal only during receptions and transmis-
sions. The SC0 pin clocks once for each bit transmitted or
received (eight clocks per transmission or reception). When the
SSIO port is idle, the pin remains either high (with handshaking)
or low (without handshaking).
Handshaking mode requires an external pull-up resistor.
I/O SSIO0 Data Pin
SD0 transmits data when SSIO0 is configured as a transmitter
and receives data when it is configured as a receiver.
I/O SSIO1 Clock Pin
This pin transmits a clock signal when SSIO1 is configured as a
master and receives a clock signal when it is configured as a
slave.
SC1 carries a clock signal only during receptions and transmis-
sions. This pin carries a clock signal only during receptions and
transmissions. The SC1 pin clocks once for each bit transmitted
or received (eight clocks per transmission or reception). When
the SSIO port is idle, the pin remains either high (with
handshaking) or low (without handshaking).
I/O SSIO1 Data Pin
SD1 transmits data when SSIO1 is configured as a transmitter
and receives data when it is configured as a receiver.
0013H Interrupt Mask 1
Setting the SSIO0 bit of this register enables the SSIO channel 0
transfer interrupt; clearing the bit disables (masks) the interrupt.
Setting the SSIO1 bit of this register enables the SSIO channel 1
transfer interrupt; clearing the bit disables (masks) the interrupt.
Description
Description