Intel 8XC196K Series User Manual page 19

CONTENTS
Table
6-7 Logic Table for Bidirectional Ports in Special-function Mode .......................................6-9
6-8 Control Register Values for Each Configuration.........................................................6-11
6-9 Port Configuration Example .......................................................................................6-11
6-10 Port Pin States After Reset and After Example Code Execution................................6-12
6-11 Ports 3 and 4 Pins ......................................................................................................6-16
6-12 Ports 3 and 4 Control and Status Registers ...............................................................6-16
6-13 Logic Table for Ports 3 and 4 as I/O...........................................................................6-18
7-1 Serial Port Signals ........................................................................................................7-2
7-2 Serial Port Control and Status Registers......................................................................7-2
7-3 SP_BAUD Values When Using XTAL1 at 16 MHz.....................................................7-12
8-1 SSIO Port Signals ........................................................................................................8-2
8-2 SSIO Port Control and Status Registers ......................................................................8-2
8-3 Common SSIO_BAUD Values at 16 MHz ....................................................................8-9
9-1 Slave Port Signals ........................................................................................................9-4
9-2 Slave Port Control and Status Registers ......................................................................9-4
9-3 Master and Slave Interconnections ..............................................................................9-6
10-1 EPA Channels ............................................................................................................10-1
10-2 EPA and Timer/Counter Signals.................................................................................10-3
10-3 EPA Control and Status Registers .............................................................................10-3
10-4 Quadrature Mode Truth Table ....................................................................................10-8
10-5 Action Taken when a Valid Edge Occurs .................................................................10-12
10-6 Example Control Register Settings and EPA Operations.........................................10-20
10-7 EPAIPV Interrupt Priority Values ..............................................................................10-30
11-1 A/D Converter Pins.....................................................................................................11-2
11-2 A/D Control and Status Registers...............................................................................11-2
12-1 CAN Controller Signals...............................................................................................12-3
12-2 Control and Status Registers .....................................................................................12-3
12-3 CAN Controller Address Map .....................................................................................12-5
12-4 Message Object Structure ..........................................................................................12-6
12-5 Effect of Masking on Message Identifiers...................................................................12-7
12-6 Standard Message Frame ..........................................................................................12-8
12-7 Extended Message Frame .........................................................................................12-8
12-8 CAN Protocol Bit Time Segments ............................................................................12-10
12-9 CAN Controller Bit Time Segments ..........................................................................12-11
12-10 Bit Timing Relationships ...........................................................................................12-12
12-11 Bit Timing Requirements for Synchronization ..........................................................12-17
12-12 Control Register Bit-pair Interpretation .....................................................................12-23
12-13 Cross-reference for Register Bits Shown in Flowcharts ...........................................12-35
12-14 Register Values Following Reset..............................................................................12-41
13-1 Minimum Required Signals.........................................................................................13-1
13-2 I/O Port Configuration Guide ......................................................................................13-2
14-1 Operating Mode Control Signals ................................................................................14-1
14-2 Operating Mode Control and Status Registers...........................................................14-2
14-3 ONCE# Pin Alternate Functions.................................................................................14-9
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TABLES
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