Servicing The Multiplexed Epa Interrupt With Software - Intel 8XC196K Series User Manual

EPA_PEND1
When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt
pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
7
— —
Bit
Number
7:4 Reserved; always write as zeros.
Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
3:0
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
Figure 10-15. EPA Interrupt Pending 1 (EPA_PEND1) Registers

10.8 SERVICING THE MULTIPLEXED EPA INTERRUPT WITH SOFTWARE

The multiplexed interrupts (those represented by EPAx) should be serviced with a standard inter-
rupt service routine rather than the PTS (Chapter 5, "Standard and PTS Interrupts"). The PTS can
take only a limited number of actions, while interrupt service routines can be tailored to the needs
of each interrupt.
The EPA_PEND (Figure 10-14) and EPA_PEND1 (Figure 10-15) registers contain the bits that
identify the interrupt source(s). Traditionally, software would sort these bits to determine which
interrupt service routine to execute. This sorting increases the overall interrupt response time by
a significant number of states. However, the EPA interrupt priority vector register (EPAIPV, Fig-
ure 10-16) contains a number that corresponds to the highest-priority active interrupt source (Ta-
ble 10-7).
For example, assume that an overrun occurs on capture/compare channel 9 and no other multi-
plexed interrupt is pending and unmasked. This sets the OVR9 pending bit in the EPA_PEND
register. If the corresponding mask bit is set in the EPA_MASK register, the EPAx interrupt pend-
ing bit is set. If enabled, the EPAx interrupt is generated. The encoder places the number for the
OVR9 interrupt (05H) into EPAIPV. Reading EPAIPV identifies capture/compare channel 9 as
the source, clears the OVR9 pending bit, and clears EPAIPV. When the device vectors to the EPAx
interrupt service routine, the EPAx pending bit is cleared. If other multiplexed interrupts have oc-
curred, the encoder loads the number that corresponds to the highest-priority, active, multiplexed
interrupt into EPAIPV. When the EPAIPV register contains 00H, there are no more pending in-
terrupts associated with the EPAx interrupt. Thus, it is recommended that the EPAIPV register be
read until it equals 00H to ensure that all pending, enabled interrupts are serviced.
— — COMP0
Function
EVENT PROCESSOR ARRAY (EPA)
Address:
Reset State:
COMP1 OVRTM1
1FA6H
00H
0
OVRTM2
10-29