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If a status change generated the interrupt (CAN_INT = 01H), software can read the CAN status
register (Figure 12-20) to determine the source of the interrupt request.
CAN_STAT
(87C196CA)
The CAN status (CAN_STAT) register reflects the current status of the CAN peripheral.
7
87C196CA
BUSOFF
Bit
Bit
Number
Mnemonic
7
BUSOFF
6
WARN
5
—
4
RXOK
3
TXOK
2:0
LEC2:0
CAN SERIAL COMMUNICATIONS CONTROLLER
WARN
—
Bus-off Status
The CAN peripheral sets this read-only bit to indicate that it has isolated
itself from the CAN bus (floated the TX pin) because an error counter has
reached 256. A bus-off recovery sequence clears this bit and clears the
error counters. (See "Bus-off State" on page 12-41.)
Warning Status
The CAN peripheral sets this read-only bit to indicate that an error counter
has reached 96, indicating an abnormal rate of errors on the CAN bus.
Reserved. This bit is undefined.
Reception Successful
The CAN peripheral sets this bit to indicate that a message has been
successfully received (error free, regardless of acknowledgment) since the
bit was last cleared. Software must clear this bit when it services the
interrupt.
Transmission Successful
The CAN peripheral sets this bit to indicate that a message has been
successfully transmitted (error free and acknowledged by at least one
other node) since the bit was last cleared. Software must clear this bit
when it services the interrupt.
Last Error Code
This field indicates the error type of the first error that occurs in a message
frame on the CAN bus. ("Error Detection and Management Logic" on page
12-9 describes the error types.)
LEC2 LEC1 LEC0 Error Type
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Figure 12-20. CAN Status (CAN_STAT) Register
RXOK
TXOK
Function
no error
stuff error
form error
acknowledgment error
bit 1 error
bit 0 error
CRC error
unused
Address:
1E01H
Reset State:
XXH
LEC2
LEC1
LEC0
0
12-33
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