Intel 8XC196K Series User Manual page 52

Follow these recommendations to help maintain hardware and software compatibility between
52-lead, 68-lead, and future devices.
•
Bus width. Since the 8XC196Jx has neither a WRH# nor a BUSWIDTH pin, the device
cannot dynamically switch between 8- and 16-bit bus widths. Program the CCBs to select 8-
bit bus mode.
•
Wait states. Since the 8XC196Jx has no READY pin, the device cannot rely on a READY
signal to control wait states. Program the CCBs to limit the number of wait states (0, 1, 2, or
3).
•
EPA4–EPA7. These functions exist in the 8XC196Jx, but the associated pins are omitted.
You can use these functions as software timers, to start A/D conversions, or to reset the
timers.
•
Slave port. Since the 8XC196Jx has no P5.1/SLPCS and P5.4/SLPINT pins, you cannot
use the slave port.
•
ONCE mode. On the 8XC196JQ and JR, the ONCE mode entry function is multiplexed
with P2.6 (P2.6/HLDA#/ONCE) rather than with P5.4 as it is on the 8XC196KQ and KR
(P5.4/SLPINT/ONCE).
•
NMI. Since the 8XC196Jx has no NMI pin, the nonmaskable interrupt is not supported.
Initialize the NMI vector (at location 203EH) to point to a RET instruction. This method
provides glitch protection only.
•
I/O ports. The following port pins do not exist in the 8XC196Jx: P0.0–P0.1, P1.4–P1.7,
P2.3 and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the
associated Px_REG, Px_MODE, and Px_DIR registers. Configure the registers for the
removed pins as follows:
— Clear the corresponding Px_DIR bits. (Configures pins as complementary outputs.)
— Clear the corresponding Px_MODE bits. (Selects I/O port function.)
— Write either "0" or "1" to the corresponding Px_REG bits. (Effectively ties signals low
or high.)
Do not use the bits associated with the removed port pins for conditional branch instruc-
tions. Treat these bits as reserved.
•
Auto programming. During auto programming, the 8XC196Jx supports only a 16-bit,
zero-wait-state bus configuration.
ARCHITECTURAL OVERVIEW
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